This file, based on one of the CAMAC support headers provides sketchy documentation of the CAMAC support macros for the NSCL DAQ system. Each CAMAC controller type has a header file. The master header <camac.h> selects between the supported camac controller header file as follows:
#define branchinit(b) #define crateinit(b, c)
#define inhibit(b,c) #define uninhibit(b,c) #define qtst(b) #define xtst(b)
#define camread16(b,c,n,a,f) #define camread24(b, c, n, a, f) #define camwrite16(b,c,n,a,f,d) #define camwrite24(b,c,n,a,f,d) #define camctl(b,c,n,a,f)
#define rdtobuf16(b, c, n, a, f) #define rdtobuf24(b, c, n, a, f)
#define qstoptobuf(b,c,n,a,f)
/* Fixed size sub event packet. */ #define Packet(size, type) #define EndPacket /* Variable sized sub event packet */ #define VPacket(type) #define EndVPacket
LAM processing
#define BEGINLAM(numbr,numcr) #define NEEDLAM(b, c, n) #define ENDLAM #define IFTIMEOUT(maxloop) #define LAMREAD(b,c) Example: ---------------------------------------------------------------------- BEGINLAM(1, 1); // Start lam wait setup NEEDLAM(0,1,5); // expect lam from slot 5. NEEDLAM(0,1,7); // expect lam from slot 7. IFTIMEOUT (100) { // Look for these lams for 100 loop passes // code if not all lams are seen } ENDLAM; // End of lam processing. ----------------------------------------------------------------------Support for Ortec AD811/TD811 ADC/TDC
This module should not be used unless unavoidable, its 80 to 160 microsecond conversion time makes it unsuitable for use in high performance systems.
#define INIT811(b, c, n) #define CLR811(b, c, n) #define READ811(b, c, n, a)Support for the LRS 22xx series of ADC, QDC, TDC modules
/* LRS 22xx series devices */ #define INIT22XX(b, c, n) #define CLR22XX(b, c, n) #define READ22XX(b, c, n, a)Support for LRS FERA QDCs
/* LRS feras. - Control register bits */ #define FERA_OFS 0x8000 #define FERA_CLE 0x4000 #define FERA_CSR 0x2000 #define FERA_CCE 0x1000 #define FERA_CPS 0x0800 #define FERA_EEN 0x0400 #define FERA_ECE 0x0200 #define FERA_EPS 0x0100 #define INITFERA(b, c, n, cmd, peds) #define CLRFERA(b, c, n) #define READFERA(b, c, n, a) #define READFERAALL(b, c, n)Support for Phillip 7xxx adc, qdc, tdc modules
/* For the 7164 ADCs: * cmd is the control register * bits 1,2,3 are ped, lower thrsh, upper thrsh enable * bits 9-16 are conversion delay * ped is the first of 16 integers for pedestals */ #define INIT7164(b,c,n,cmd,ped) #define INIT7186(b,c,n,ip,ilow,iup,ped) /* Reads and clears are straightforward * bits 12-16 contain the address, which we don't want */ #define READ7164(b,c,n,a) #define READ7186(b,c,n,a) #define CLR7164(b,c,n)Support for Silena 4418 ADCs
/* initialize Silena 4418 ADC ** Arguments: ** int b,c,n - Branch, crate, slot ** int cmd - status register ** int thrsh - number of first of 25 users integers ** common threshold x1 ** lower level discriminator x8 ** offset x8 ** upper level discriminator x8 */ #define INIT4418(b,c,n,cmd,thrsh) #define READ4418(b,c,n,a) rdtobuf16((b),(c),(n),(a), 2) #define RDHDR4418(b,c,n) camread16((b),(c),(n),14, 2) #define RDPAT4418(b,c,n) camread16((b),(c),(n),15, 2) #define BLKREAD4418(b,c,n) qstoptobuf((b),(c),(n),0, 2)Support for LRS 4448 scalers
/* LRS 4448 scalers. control register bits. */ #define ECLSCL_TEST 0x8000 #define ECLSCL_BD 0x2000 #define ECLSCL_RD 0x0080 #define ECLSCL_CL 0x0040 #define ECLSCL_LD 0X0020 #define ECLSCL_NPOS 8 #define INIT4434(b, c, n) #define CLR4434(b, c, n) #define READ4434(b, c, n, a) #define READALL4434(b, c, n)Support for LRS 2551 scalers
/* LRS 2551 scalers. */ #define INIT2551(b, c, n) #define CLR2551(b, c, n) #define READ2551(b, c, n, a) #define READALL2551(b, c, n)