NSCL DDAS  1.0
Support for XIA DDAS at the NSCL
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CMyEventSegment.h
1 #ifndef __CMYEVENTSEGMENT_H
2 #define __CMYEVENTSEGMENT_H
3 
4 #include <CExperiment.h>
5 #include <CEventSegment.h>
6 #include <CRingItem.h>
7 #include <CRingBuffer.h>
8 #include <vector>
9 #include <deque>
10 #include <fstream>
11 // event segment for the control
12 // and readout of pixie16 modules
13 // 1 crate only readout, standard firmware
14 // snl - 1/20/10
15 using namespace std;
16 
17 #define MAXMOD 14
18 #define FILENAME_STR_MAXLEN 256
19 #define MAX_NUM_PIXIE16_MODULES 24
20 #define TOTAL_PIXIE16_VARIANTS 8
21 
22 class CMyTrigger;
23 
24 class channel
25 {
26 
27 public:
28  double time;
29  int chanid;
30  int channellength;
31  vector<uint32_t> data;
32 
33  channel();
34  ~channel();
35  double GetTime() const {return time;};
36  int SetTime();
37  int SetTime(double clockcal);
38  double GetChannelLength() const {return channellength;};
39  int SetChannelLength();
40  int SetChannel();
41  int GetChannel() const {return chanid;};
42  int Validate(int);
43 };
44 
45 class CMyEventSegment : public CEventSegment
46 {
47 
48 private:
49  //any private variables
50  //CRingBuffer *ring;
51  std::ofstream ofile;
52 
53  int fragcount;
54  double globaltime;
55  double time_buffer;
56 
57  unsigned short CrateNum;
58  unsigned short NumModules;
59  unsigned short *PXISlotMap;
60  double *ModEventLen;
61  double StopTime;
62  //char ComFPGAConfigFile[80];
63  //char SPFPGAConfigFile[80];
64  //char TrigFPGAConfigFile[80];
65  //char DSPCodeFile[80];
66  char DSPParFile[80];
67  //char DSPVarFile[80];
68 
69  char ComFPGAConfigFile_RevBCD[FILENAME_STR_MAXLEN];
70  char ComFPGAConfigFile_RevF_100MHz_14Bit[FILENAME_STR_MAXLEN];
71  char ComFPGAConfigFile_RevF_100MHz_16Bit[FILENAME_STR_MAXLEN];
72  char ComFPGAConfigFile_RevF_250MHz_12Bit[FILENAME_STR_MAXLEN];
73  char ComFPGAConfigFile_RevF_250MHz_14Bit[FILENAME_STR_MAXLEN];
74  char ComFPGAConfigFile_RevF_250MHz_16Bit[FILENAME_STR_MAXLEN];
75  char ComFPGAConfigFile_RevF_500MHz_12Bit[FILENAME_STR_MAXLEN];
76  char ComFPGAConfigFile_RevF_500MHz_14Bit[FILENAME_STR_MAXLEN];
77 
78  char SPFPGAConfigFile_RevBCD[FILENAME_STR_MAXLEN];
79  char SPFPGAConfigFile_RevF_100MHz_14Bit[FILENAME_STR_MAXLEN];
80  char SPFPGAConfigFile_RevF_100MHz_16Bit[FILENAME_STR_MAXLEN];
81  char SPFPGAConfigFile_RevF_250MHz_12Bit[FILENAME_STR_MAXLEN];
82  char SPFPGAConfigFile_RevF_250MHz_14Bit[FILENAME_STR_MAXLEN];
83  char SPFPGAConfigFile_RevF_250MHz_16Bit[FILENAME_STR_MAXLEN];
84  char SPFPGAConfigFile_RevF_500MHz_12Bit[FILENAME_STR_MAXLEN];
85  char SPFPGAConfigFile_RevF_500MHz_14Bit[FILENAME_STR_MAXLEN];
86 
87  char DSPCodeFile_RevBCD[FILENAME_STR_MAXLEN];
88  char DSPCodeFile_RevF_100MHz_14Bit[FILENAME_STR_MAXLEN];
89  char DSPCodeFile_RevF_100MHz_16Bit[FILENAME_STR_MAXLEN];
90  char DSPCodeFile_RevF_250MHz_12Bit[FILENAME_STR_MAXLEN];
91  char DSPCodeFile_RevF_250MHz_14Bit[FILENAME_STR_MAXLEN];
92  char DSPCodeFile_RevF_250MHz_16Bit[FILENAME_STR_MAXLEN];
93  char DSPCodeFile_RevF_500MHz_12Bit[FILENAME_STR_MAXLEN];
94  char DSPCodeFile_RevF_500MHz_14Bit[FILENAME_STR_MAXLEN];
95 
96  char DSPVarFile_RevBCD[FILENAME_STR_MAXLEN];
97  char DSPVarFile_RevF_100MHz_14Bit[FILENAME_STR_MAXLEN];
98  char DSPVarFile_RevF_100MHz_16Bit[FILENAME_STR_MAXLEN];
99  char DSPVarFile_RevF_250MHz_12Bit[FILENAME_STR_MAXLEN];
100  char DSPVarFile_RevF_250MHz_14Bit[FILENAME_STR_MAXLEN];
101  char DSPVarFile_RevF_250MHz_16Bit[FILENAME_STR_MAXLEN];
102  char DSPVarFile_RevF_500MHz_12Bit[FILENAME_STR_MAXLEN];
103  char DSPVarFile_RevF_500MHz_14Bit[FILENAME_STR_MAXLEN];
104 
105  unsigned short ModRev[MAX_NUM_PIXIE16_MODULES]; // module revision in hex format (NSCL had D and F modules
106  unsigned short ModADCBits[MAX_NUM_PIXIE16_MODULES]; // adc bits of a module
107  unsigned short ModADCMSPS[MAX_NUM_PIXIE16_MODULES]; // sampling rate of a module
108  unsigned int ModSerNum[MAX_NUM_PIXIE16_MODULES]; // module serial number
109  unsigned int ModuleRevBitMSPSWord[MAX_NUM_PIXIE16_MODULES]; //word to store rev, bit depth, and MSPS of module for insertion into the data stream.
110  unsigned int ModClockCal[MAX_NUM_PIXIE16_MODULES]; //word to calibration between clock ticks and nanoseconds.
111  char Pixie16_Com_FPGA_File[FILENAME_STR_MAXLEN];
112  char Pixie16_SP_FPGA_File[FILENAME_STR_MAXLEN];
113  char Pixie16_DSP_Code_File[FILENAME_STR_MAXLEN];
114  char Pixie16_DSP_Var_File[FILENAME_STR_MAXLEN];
115  char Pixie16_Trig_FPGA_File[FILENAME_STR_MAXLEN];
116 
117  int retval;
118  int count;
119  char filnam[80];
120  unsigned int nFIFOWords;
121  //unsigned long *lmdata;
122  //unsigned long mod_numwordsread;
123  unsigned short EndOfRunRead;
124 
125  unsigned int *CrateData;
126  unsigned int **PositionInCrateData;
127  unsigned long totwords;
128  vector<unsigned int *> ChannelList;
129  vector<unsigned int *>::iterator ChannelList_it;
130 
131  //deque<uint32_t> ModuleDeque[MAXMOD];
132  deque<channel *> ModuleDeque[MAXMOD];
133  deque<channel *> ModuleDequeTemp;
134  vector<uint32_t> ModuleData[MAXMOD];
135 
136  vector<uint32_t> DataToWorld;
137 
138  vector<uint32_t> nFIFOWordsinModuleCurrentRead;
139  vector<uint64_t> nFIFOWordsinModuleTotal;
140 
141 
142  vector<double> CurrentTimeinModuleRead;
143  vector<double> FirstTimeinModuleRead;
144 
145  unsigned long CurrentTime;
146  unsigned long lasttime;
147  unsigned long TimeWindow;
148 
149 
150  bool m_processing;
151  bool processdata;
152 
153  CMyTrigger *mytrigger;
154 
155 public:
157  ~CMyEventSegment();
158 
159  virtual void initialize();
160  //virtual DAQWordBufferPtr& Read(DAQWordBufferPtr& rBuffer);
161  virtual size_t read(void* rBuffer, size_t maxwords);
162  virtual void disable();
163  virtual void clear();
164 
165  virtual void onEnd(CExperiment* pExperiment);
166  int GetNumberOfModules() {return (int)NumModules;}
167  unsigned short GetCrateID() {return CrateNum;}
168 
169  bool IsUniqueEvent(const channel* event);
170  void synchronize();
171 
172 private:
173  size_t SelectivelyOutputData(void* rBuffer, size_t maxwords);
174  bool DataToRead();
175  void PushDataOntoQueue(std::deque<channel*>& deque, std::deque<channel*>& buffer);
176 };
177 #endif