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xiaapi
inc
PciRegs.h
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#ifndef __PCI_REGS_H
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#define __PCI_REGS_H
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/*******************************************************************************
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* Copyright (c) PLX Technology, Inc.
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*
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* PLX Technology Inc. licenses this source file under the GNU Lesser General Public
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* License (LGPL) version 2. This source file may be modified or redistributed
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* under the terms of the LGPL and without express permission from PLX Technology.
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*
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* PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY,
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* EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee
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* or representations regarding the use of, or the results of the use of,
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* the software and documentation in terms of correctness, accuracy,
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* reliability, currentness, or otherwise; and you rely on the software,
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* documentation and results solely at your own risk.
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*
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* IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
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* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
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* OF ANY KIND.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* File Name:
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*
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* PciRegs.h
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*
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* Description:
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*
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* This file defines the generic PCI Configuration Registers
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*
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* Revision:
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*
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* 05-01-13 : PLX SDK v7.10
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*
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******************************************************************************/
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// PCI Extended Capability IDs
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#define CAP_ID_POWER_MAN 0x01
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#define CAP_ID_AGP 0x02
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#define CAP_ID_VPD 0x03
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#define CAP_ID_SLOT_ID 0x04
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#define CAP_ID_MSI 0x05
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#define CAP_ID_HOT_SWAP 0x06
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#define CAP_ID_PCIX 0x07
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#define CAP_ID_HYPER_TRANSPORT 0x08
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#define CAP_ID_VENDOR_SPECIFIC 0x09
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#define CAP_ID_DEBUG_PORT 0x0A
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#define CAP_ID_RESOURCE_CTRL 0x0B
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#define CAP_ID_HOT_PLUG 0x0C
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#define CAP_ID_BRIDGE_SUB_ID 0x0D
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#define CAP_ID_AGP_8X 0x0E
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#define CAP_ID_SECURE_DEVICE 0x0F
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#define CAP_ID_PCI_EXPRESS 0x10
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#define CAP_ID_MSI_X 0x11
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#define CAP_ID_SATA 0x12
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#define CAP_ID_ADV_FEATURES 0x13
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// PCI Express Extended Capability IDs
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#define PCIE_CAP_ID_ADV_ERROR_REPORTING 0x001 // Advanced Error Reporting
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#define PCIE_CAP_ID_VIRTUAL_CHANNEL 0x002 // Virtual Channel
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#define PCIE_CAP_ID_DEV_SERIAL_NUMBER 0x003 // Device Serial Number
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#define PCIE_CAP_ID_POWER_BUDGETING 0x004 // Power Budgeting
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#define PCIE_CAP_ID_RC_LINK_DECLARATION 0x005 // Root Complex Link Declaration
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#define PCIE_CAP_ID_RC_INT_LINK_CONTROL 0x006 // Root Complex Internal Link Control
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#define PCIE_CAP_ID_RC_EVENT_COLLECTOR 0x007 // Root Complex Event Collector Endpoint Association
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#define PCIE_CAP_ID_MF_VIRTUAL_CHANNEL 0x008 // Multi-Function Virtual Channel
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#define PCIE_CAP_ID_VC_WITH_MULTI_FN 0x009 // Virtual Channel with Multi-Function
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#define PCIE_CAP_ID_RC_REG_BLOCK 0x00A // Root Complex Register Block
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#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x00B // Vendor-specific
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#define PCIE_CAP_ID_CONFIG_ACCESS_CORR 0x00C // Configuration Access Correlation
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#define PCIE_CAP_ID_ACCESS_CTRL_SERVICES 0x00D // Access Control Services
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#define PCIE_CAP_ID_ALT_ROUTE_ID_INTERPRET 0x00E // Alternate Routing-ID Interpretation
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#define PCIE_CAP_ID_SR_IOV 0x010 // SR-IOV
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#define PCIE_CAP_ID_MR_IOV 0x011 // MR-IOV
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#define PCIE_CAP_ID_MULTICAST 0x012 // Multicast
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#define PCIE_CAP_ID_RESIZABLE_BAR 0x015 // Resizable BAR
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#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOC 0x016 // Dynamic Power Allocation
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#define PCIE_CAP_ID_TLP_PROCESSING_HINT 0x017 // TLP Processing Hint (TPH) Requester
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#define PCIE_CAP_ID_LATENCY_TOLERANCE_REPORT 0x018 // Latency Tolerance Reporting
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#define PCIE_CAP_ID_SECONDARY_PCI_EXPRESS 0x019 // Secondary PCI Express
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#define PCIE_CAP_ID_PROTOCOL_MULTIPLEX 0x01A // Protocol Multiplexing (PMUX)
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#define PCIE_CAP_ID_PROCESS_ADDR_SPACE_ID 0x01B // Process Address Space ID (PASID)
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#define PCIE_CAP_ID_LTWT_NOTIF_REQUESTER 0x01C // Lightweight Notification Requester (LNR)
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#define PCIE_CAP_ID_DS_PORT_CONTAINMENT 0x01D // Downstream Port Containment (DPC)
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#define PCIE_CAP_ID_L1_PM_SUBSTRATES 0x01E // L1 Power Management Substrates (L1PM)
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#define PCIE_CAP_ID_PRECISION_TIME_MEAS 0x01F // Precision Time Measurement (PTM)
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// Function codes for PCI BIOS operations
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#define PCI_FUNC_ID 0xb1
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#define PCI_FUNC_BIOS_PRESENT 0x01
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#define PCI_FUNC_FIND_PCI_DEVICE 0x02
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#define PCI_FUNC_FIND_PCI_CLASS_CODE 0x03
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#define PCI_FUNC_GENERATE_SPECIAL_CYC 0x06
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#define PCI_FUNC_READ_CONFIG_BYTE 0x08
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#define PCI_FUNC_READ_CONFIG_WORD 0x09
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#define PCI_FUNC_READ_CONFIG_DWORD 0x0a
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#define PCI_FUNC_WRITE_CONFIG_BYTE 0x0b
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#define PCI_FUNC_WRITE_CONFIG_WORD 0x0c
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#define PCI_FUNC_WRITE_CONFIG_DWORD 0x0d
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#define PCI_FUNC_GET_IRQ_ROUTING_OPTS 0x0e
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#define PCI_FUNC_SET_PCI_HW_INT 0x0f
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#endif
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