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xiaapi
inc
Plx.h
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#ifndef __PLX_H
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#define __PLX_H
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/*******************************************************************************
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* Copyright (c) PLX Technology, Inc.
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*
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* PLX Technology Inc. licenses this source file under the GNU Lesser General Public
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* License (LGPL) version 2. This source file may be modified or redistributed
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* under the terms of the LGPL and without express permission from PLX Technology.
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*
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* PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY,
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* EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee
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* or representations regarding the use of, or the results of the use of,
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* the software and documentation in terms of correctness, accuracy,
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* reliability, currentness, or otherwise; and you rely on the software,
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* documentation and results solely at your own risk.
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*
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* IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
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* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
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* OF ANY KIND.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* File Name:
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*
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* Plx.h
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*
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* Description:
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*
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* This file contains definitions that are common to all PCI SDK code
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*
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* Revision:
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*
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* 04-01-13 : PLX SDK v7.10
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*
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******************************************************************************/
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/**********************************************
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* Definitions
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**********************************************/
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// SDK Version information
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#define PLX_SDK_VERSION_MAJOR 7
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#define PLX_SDK_VERSION_MINOR 10
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#define PLX_SDK_VERSION_STRING "7.10"
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#define PLX_SDK_COPYRIGHT_STRING "\251 PLX Technology, Inc. 2013"
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#define MAX_PCI_BUS 255 // Max PCI Buses
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#define MAX_PCI_DEV 32 // Max PCI Slots
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#define MAX_PCI_FUNC 8 // Max PCI Functions
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#define PCI_NUM_BARS_TYPE_00 6 // Total PCI BARs for Type 0 Header
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#define PCI_NUM_BARS_TYPE_01 2 // Total PCI BARs for Type 1 Header
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#define PLX_VENDOR_ID 0x10B5 // PLX Vendor ID
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// Device object validity codes
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#define PLX_TAG_VALID 0x5F504C58 // "_PLX" in Hex
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#define PLX_TAG_INVALID 0x564F4944 // "VOID" in Hex
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#define ObjectValidate(pObj) ((pObj)->IsValidTag = PLX_TAG_VALID)
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#define ObjectInvalidate(pObj) ((pObj)->IsValidTag = PLX_TAG_INVALID)
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#define IsObjectValid(pObj) ((pObj)->IsValidTag == PLX_TAG_VALID)
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// Used for locating PCI devices
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#define PCI_FIELD_IGNORE (-1)
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// Used for VPD accesses
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#define VPD_COMMAND_MAX_RETRIES 5 // Max number VPD command re-issues
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#define VPD_STATUS_MAX_POLL 10 // Max number of times to read VPD status
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#define VPD_STATUS_POLL_DELAY 5 // Delay between polling VPD status (Milliseconds)
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// Define a large value for a signal to the driver
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#define FIND_AMOUNT_MATCHED 80001
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// Used for performance counter calculations
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#define PERF_TLP_OH_DW 2 // Overhead DW per TLP
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#define PERF_TLP_DW (3 + PERF_TLP_OH_DW) // DW per TLP
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#define PERF_TLP_SIZE (PERF_TLP_DW * sizeof(U32)) // Bytes per TLP w/o payload
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#define PERF_DLLP_SIZE (2 * sizeof(U32)) // Bytes per DLLP
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#define PERF_MAX_BPS_GEN_1_0 ((U64)250000000) // 250 MBps (2.5 Gbps * 80%)
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#define PERF_MAX_BPS_GEN_2_0 ((U64)500000000) // 500 MBps (5 Gbps * 80%)
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#define PERF_MAX_BPS_GEN_3_0 ((U64)1000000000) // 1 GBps (8 Gbps)
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// Endian swap macros
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#define EndianSwap32(value) ( ((((value) >> 0) & 0xff) << 24) | \
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((((value) >> 8) & 0xff) << 16) | \
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((((value) >> 16) & 0xff) << 8) | \
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((((value) >> 24) & 0xff) << 0) )
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#define EndianSwap16(value) ( ((((value) >> 0) & 0xffff) << 16) | \
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((((value) >> 16) & 0xffff) << 0) )
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// PCIe ReqID support macros
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#define Plx_PciToReqId(bus,slot,fn) (((U16)bus << 8) | (slot << 3) | (fn << 0))
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#define Plx_ReqId_Bus(ReqId) ((U8)(ReqId >> 8) & 0xFF)
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#define Plx_ReqId_Slot(ReqId) ((U8)(ReqId >> 3) & 0x1F)
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#define Plx_ReqId_Fn(ReqId) ((U8)(ReqId >> 0) & 0x7)
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// Device IDs of PLX reference boards
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#define PLX_9080RDK_960_DEVICE_ID 0x0960
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#define PLX_9080RDK_401B_DEVICE_ID 0x0401
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#define PLX_9080RDK_860_DEVICE_ID 0x0860
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#define PLX_9054RDK_860_DEVICE_ID 0x1860
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#define PLX_9054RDK_LITE_DEVICE_ID 0x5406
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#define PLX_CPCI9054RDK_860_DEVICE_ID 0xC860
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#define PLX_9056RDK_LITE_DEVICE_ID 0x5601
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#define PLX_9056RDK_860_DEVICE_ID 0x56c2
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#define PLX_9656RDK_LITE_DEVICE_ID 0x9601
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#define PLX_9656RDK_860_DEVICE_ID 0x96c2
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#define PLX_9030RDK_LITE_DEVICE_ID 0x3001
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#define PLX_CPCI9030RDK_LITE_DEVICE_ID 0x30c1
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#define PLX_9050RDK_LITE_DEVICE_ID 0x9050
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#define PLX_9052RDK_LITE_DEVICE_ID 0x5201
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#ifdef __cplusplus
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}
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#endif
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#endif
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