NSCL DDAS
1.0
Support for XIA DDAS at the NSCL
Main Page
User Guides
Classes
Files
File List
File Members
All
Classes
Files
Functions
Variables
Macros
Pages
xiaapi
app
pixie16app_defs.h
1
#ifndef __PIXIE16APP_DEFS_H
2
#define __PIXIE16APP_DEFS_H
3
4
/*----------------------------------------------------------------------
5
* Copyright (c) 2005 - 2009, XIA LLC
6
* All rights reserved.
7
*
8
* Redistribution and use in source and binary forms,
9
* with or without modification, are permitted provided
10
* that the following conditions are met:
11
*
12
* * Redistributions of source code must retain the above
13
* copyright notice, this list of conditions and the
14
* following disclaimer.
15
* * Redistributions in binary form must reproduce the
16
* above copyright notice, this list of conditions and the
17
* following disclaimer in the documentation and/or other
18
* materials provided with the distribution.
19
* * Neither the name of XIA LLC nor the names of its
20
* contributors may be used to endorse or promote products
21
* derived from this software without specific prior
22
* written permission.
23
*
24
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
25
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
26
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28
* IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
29
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
34
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
35
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36
* SUCH DAMAGE.
37
*----------------------------------------------------------------------*/
38
39
/******************************************************************************
40
*
41
* File Name:
42
*
43
* pixie16app_defs.h
44
*
45
* Description:
46
*
47
* Constant definitions.
48
*
49
* $Rev: 31427 $
50
* $Id: pixie16app_defs.h 31427 2014-11-24 23:49:28Z htan $
51
******************************************************************************/
52
53
/* If this is compiled by a C++ compiler, make it */
54
/* clear that these are C routines. */
55
#ifdef __cplusplus
56
extern
"C"
{
57
#endif
58
59
60
/*-------------------------------------
61
At which platform to compile this code -
62
Windows or Linux?
63
-------------------------------------*/
64
#define PIXIE16_WINDOWS_APPAPI 0
65
#define PIXIE16_LINUX_APPAPI 1
66
// Changing PIXIE16_APPAPI_VER here affects the code globally
67
#define PIXIE16_APPAPI_VER PIXIE16_LINUX_APPAPI
68
69
70
/*-------------------------------------
71
Define EXPORT macro
72
-------------------------------------*/
73
#if PIXIE16_APPAPI_VER == PIXIE16_WINDOWS_APPAPI
74
#define PIXIE16APP_EXPORT __declspec(dllexport)
75
#define PIXIE16APP_API _stdcall
76
#elif PIXIE16_APPAPI_VER == PIXIE16_LINUX_APPAPI
77
#define PIXIE16APP_EXPORT
78
#define PIXIE16APP_API
79
#endif
80
81
82
/*-------------------------------------
83
Define math constants
84
-------------------------------------*/
85
86
#ifndef PI
87
#define PI 3.14159265358979
88
#endif
89
90
#ifndef PI2
91
#define PI2 6.28318530717959
92
#endif
93
94
95
/*-------------------------------------
96
Define boot patterns
97
-------------------------------------*/
98
#define BOOTPATTERN_COMFPGA_BIT 0
99
#define BOOTPATTERN_SPFPGA_BIT 2
100
#define BOOTPATTERN_DSPCODE_BIT 3
101
#define BOOTPATTERN_DSPPAR_BIT 4
102
#define BOOTPATTERN_PROGFIPPI_BIT 5
103
#define BOOTPATTERN_SETDACS_BIT 6
104
105
106
/*-----------------------------------------------------------------
107
size of system FPGA, trigger FPGA, Fippi, DSP parameters files
108
-----------------------------------------------------------------*/
109
110
// Rev-B, C, D
111
#define N_COM_FPGA_CONF_REVBCD 162962 // size of communications FPGA configuration (32-bit word)
112
#define N_SP_FPGA_CONF_REVBCD 162962 // size of signal processing FPGA configuration (32-bit word)
113
114
// Rev-F
115
#define N_COM_FPGA_CONF_REVF 162962 // size of communications FPGA configuration (32-bit word)
116
#define N_SP_FPGA_CONF_REVF 371101 // size of signal processing FPGA configuration (32-bit word)
117
118
119
#define N_DSP_PAR 1280 // number of DSP parameters (32-bit word)
120
#define DSP_IO_BORDER 832 // number of DSP I/O variables
121
122
123
/*-----------------------------------------------------------------
124
module specifications
125
-----------------------------------------------------------------*/
126
127
#define PRESET_MAX_MODULES 24 // Preset maximum number of Pixie modules
128
#define NUMBER_OF_CHANNELS 16
129
130
131
#define DSP_CLOCK_MHZ 100 // DSP clock frequency in MHz
132
#define SYSTEM_CLOCK_MHZ 100 // System FPGA clock frequency in MHz (used for real time counting)
133
134
#define DAC_VOLTAGE_RANGE 3.0 // Pixie-16 DAC range is -1.5 V to +1.5 V
135
136
#define MAX_ADC_TRACE_LEN 8192 // Maximum ADC trace length for a channel
137
138
/*-----------------------------------------------------------------
139
run type
140
-----------------------------------------------------------------*/
141
142
#define NEW_RUN 1 // New data run
143
#define RESUME_RUN 0 // Resume run
144
145
#define LIST_MODE_RUN 0x100 // List mode run
146
#define HISTOGRAM_RUN 0x301 // Histogram run
147
148
149
/*-----------------------------------------------------------------
150
I/O mode
151
-----------------------------------------------------------------*/
152
153
#define MOD_READ 1 // Host read from modules
154
#define MOD_WRITE 0 // Host write to modules
155
156
157
/*-----------------------------------------------------------------
158
Data memory, buffer, histogram, and list mode data structure
159
-----------------------------------------------------------------*/
160
161
#define DSP_IMBUFFER_START_ADDR 0x40000 // 32-bit wide
162
#define DSP_IMBUFFER_END_ADDR 0x5FFFF // 32-bit wide
163
164
#define DSP_EMBUFFER_START_ADDR 0x0 // 32-bit wide
165
#define DSP_EMBUFFER_END_ADDR 0x7FFFF // 32-bit wide
166
167
#define DATA_MEMORY_ADDRESS 0x4A000 // DSP data memory address
168
#define HISTOGRAM_MEMORY_ADDRESS 0x0 // histogram memory buffer in external memory
169
#define MAX_HISTOGRAM_LENGTH 32768 // Maximum MCA histogram length
170
#define IO_BUFFER_ADDRESS 0x50000 // Address of I/O output buffer
171
#define IO_BUFFER_LENGTH 65536 // Length of I/O output buffer
172
#define EXTERNAL_FIFO_LENGTH 131072 // Length of external FIFO
173
174
#define EVENT_INFO_LENGTH 68 // Information length for each event
175
#define CHANNEL_INFO_LENGTH 4 // Information length for each channel
176
#define EVENT_INFO_HEADER_LENGTH 4 // Information length for each event header
177
178
179
/*-------------------------------------
180
Length limits for certain DSP parameters
181
--------------------------------------*/
182
183
#define FASTFILTER_MAX_LEN 127
184
#define FAST_THRESHOLD_MAX 65535
185
#define MIN_FASTLENGTH_LEN 2
186
187
#define SLOWFILTER_MAX_LEN 127
188
#define MIN_SLOWLENGTH_LEN 2
189
#define MIN_SLOWGAP_LEN 3
190
191
#define FASTFILTERRANGE_MAX 0
192
#define FASTFILTERRANGE_MIN 0
193
194
#define SLOWFILTERRANGE_MAX 6
195
#define SLOWFILTERRANGE_MIN 1
196
197
#define FASTTRIGBACKLEN_MAX 4095
198
#define FASTTRIGBACKLEN_MIN_100MHZFIPCLK 1
199
#define FASTTRIGBACKLEN_MIN_125MHZFIPCLK 2
200
201
#define CFDDELAY_MAX 63
202
#define CFDDELAY_MIN 1
203
204
#define CFDSCALE_MAX 15
205
206
#define CFDTHRESH_MAX 65535
207
#define CFDTHRESH_MIN 1
208
209
#define EXTTRIGSTRETCH_MAX 4095
210
#define EXTTRIGSTRETCH_MIN 1
211
212
#define VETOSTRETCH_MAX 4095
213
#define VETOSTRETCH_MIN 1
214
215
#define EXTDELAYLEN_MAX_REVBCD 255
216
#define EXTDELAYLEN_MAX_REVF 511
217
#define EXTDELAYLEN_MIN 0
218
219
#define FASTTRIGBACKDELAY_MAX_REVBCD 255
220
#define FASTTRIGBACKDELAY_MAX_REVF 511
221
#define FASTTRIGBACKDELAY_MIN 0
222
223
#define QDCLEN_MAX 32767
224
#define QDCLEN_MIN 1
225
226
#define TRACELEN_MIN_500MHZADC 10
227
#define TRACELEN_MIN_250OR100MHZADC 4
228
229
#define TRACEDELAY_MAX 1023
230
231
#define CHANTRIGSTRETCH_MAX 4095
232
#define CHANTRIGSTRETCH_MIN 1
233
234
/*-------------------------------------
235
CHANCSRA bits definitions
236
--------------------------------------*/
237
238
#define CCSRA_FTRIGSEL 0 // fast trigger selection - 1: select external fast trigger; 0: select group trigger
239
#define CCSRA_EXTTRIGSEL 1 // module validation signal selection - 1: select module gate signal; 0: select global validation signal (RevD & RevF only)
240
#define CCSRA_GOOD 2 // good-channel bit - 1: channel data will be read out; 0: channel data will not be read out
241
#define CCSRA_CHANTRIGSEL 3 // channel validation signal selection - 1: select channel gate signal; 0: select channel validation signal (RevD & RevF only)
242
#define CCSRA_SYNCDATAACQ 4 // block data acquisition if trace or header DPMs are full - 1: enable; 0: disable
243
#define CCSRA_POLARITY 5 // input signal polarity control
244
#define CCSRA_VETOENA 6 // veto channel trigger - 1: enable; 0: disable
245
#define CCSRA_HISTOE 7 // histogram energy in the on-board MCA
246
#define CCSRA_TRACEENA 8 // trace capture and associated header data - 1: enable; 0: disable
247
#define CCSRA_QDCENA 9 // QDC summing and associated header data - 1: enable; 0: dsiable
248
#define CCSRA_CFDMODE 10 // CFD for real time, trace capture and QDC capture - 1: enable; 0: disable
249
#define CCSRA_GLOBTRIG 11 // global trigger for validation - 1: enable; 0: disable
250
#define CCSRA_ESUMSENA 12 // raw energy sums and baseline in event header - 1: enable; 0: disable
251
#define CCSRA_CHANTRIG 13 // channel trigger for validation - 1: enable; 0: disable
252
#define CCSRA_ENARELAY 14 // Control input relay: 1: connect, 0: disconnect
253
254
// Control pileup rejection using bit 15 and 16 of ChanCSRA:
255
// bits[16:15]
256
// 00: record all events (trace, timestamps, etc., but no energy for piled-up events)
257
// 01: only record single events (trace, energy, timestamps, etc.) (i.e., reject piled-up events)
258
// 10: record trace, timestamps, etc., for piled-up events but do not record trace for single events
259
// 11: only record trace, timestamps, etc., for piled-up events (i.e., reject single events)
260
#define CCSRA_PILEUPCTRL 15
261
#define CCSRA_INVERSEPILEUP 16
262
263
#define CCSRA_ENAENERGYCUT 17 // Enable "no trace for large pulses" feature - 1: enable; 0: disable
264
#define CCSRA_GROUPTRIGSEL 18 // Group trigger selection - 1: external group trigger; 0: local fast trigger
265
#define CCSRA_CHANVETOSEL 19 // Channel veto selection - 1: channel validation trigger; 0: front panel channel veto
266
#define CCSRA_MODVETOSEL 20 // Module veto selection - 1: module validation trigger; 0: front panel module veto
267
#define CCSRA_EXTTSENA 21 // External timestamps in event header - 1: enable; 0: disable
268
269
/*-------------------------------------
270
MODCSRB bits definitions
271
--------------------------------------*/
272
273
#define MODCSRB_CPLDPULLUP 0 // Control pullups for PXI trigger lines on the backplane through CPLD
274
#define MODCSRB_DIRMOD 4 // Set this module as the Director module (1) or non-Director module (0)
275
#define MODCSRB_CHASSISMASTER 6 // Control chassis master module: 1: chassis master module; 0: chassis non-master module
276
#define MODCSRB_GFTSEL 7 // Select global fast trigger source
277
#define MODCSRB_ETSEL 8 // Select external trigger source
278
#define MODCSRB_INHIBITENA 10 // Control external INHIBIT signal: use INHIBIT (1) or don't use INHIBIT (0)
279
#define MODCSRB_MULTCRATES 11 // Distribute clock and triggers in multiple crates: multiple crates (1) or only single crate (0)
280
#define MODCSRB_SORTEVENTS 12 // Sort (1) or don't sort events based on their timestamps
281
#define MODCSRB_BKPLFASTTRIG 13 // Enable connection of fast triggers to backplane
282
283
/*-------------------------------------
284
CPLD CSR bits definitions
285
--------------------------------------*/
286
287
#define CPLDCSR_PULLUP 13 // Control backplane pullups: 1: pulled up, 0: not pulled up
288
289
290
/*-------------------------------------
291
Control parameters
292
--------------------------------------*/
293
294
#define MAX_PAR_NAME_LENGTH 65 // Maximum length of parameter names
295
#define RANDOMINDICES_LENGTH 8192 // number of random indices (currently only used for tau finder)
296
#define MAX_ERRMSG_LENGTH 1024 // Maximum length of error message
297
298
#define BASELINES_BLOCK_LEN 18 // Length of each baselines length (default: 2 timestamp words + 16 baselines)
299
#define MAX_NUM_BASELINES 3640 // Maximum number of baselines available after each baseline acquisition run
300
#define MAX_NUM_DCVALUES 16384 // Maximum number of DC values available after each RampOffsetDACs run
301
302
#define EXTFIFO_READ_THRESH 1024 // Reading out threshold for external FIFO watermmark level
303
304
#define PCI_STOPRUN_REGADDR 0x44 // PCI register address in the System FPGA for stopping run
305
306
/*-------------------------------------
307
Frequently used Control Tasks
308
--------------------------------------*/
309
310
#define SET_DACS 0 // Set DACs
311
#define ENABLE_INPUT 1 // Enable detect signal input
312
#define RAMP_OFFSETDACS 3 // Ramp Offset DACs
313
#define GET_TRACES 4 // Acquire ADC traces
314
#define PROGRAM_FIPPI 5 // Program FIPPIs
315
#define GET_BASELINES 6 // Get baselines
316
#define ADJUST_OFFSETS 7 // Adjust DC-offsets
317
#define TAU_FINDER 8 // Find decay time Tau
318
319
#define RESET_ADC 23 // Reset ADCs
320
321
#ifdef __cplusplus
322
}
323
#endif
324
325
#endif
Generated on Mon Aug 1 2016 11:33:25 for NSCL DDAS by
1.8.1.2