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xiaapi
inc
def21160.h
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/************************************************************************
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*
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* def21160.h
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*
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* (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved.
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* $Revision: 1.10 $
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************************************************************************/
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/* -----------------------------------------------------------------------------
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def21160.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21160
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Last Modification on: $Date: 2004/03/11 10:31:19 $
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This include file contains a list of macro "defines" to enable the programmer
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to use symbolic names for the following ADSP-21160 facilities:
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- instruction condition codes
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- system register bit definitions
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- IOP register map
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- *some* IOP register bit definitions
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Here are some example uses:
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bit set mode1 BR0|IRPTEN|ALUSTAT;
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ustat1=BSO|HPM01|HMSWF;
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DM(SYSCON)=ustat1;
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Modified on 8/12/02 - 'Completed' bit definitions. Changed to bit names rather
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than hex values.
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--------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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/* ADSP-21160 definitions */
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#ifndef __DEF21160_H_
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#define __DEF21160_H_
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#define BIT_0 0x00000001
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#define BIT_1 0x00000002
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#define BIT_2 0x00000004
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#define BIT_3 0x00000008
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#define BIT_4 0x00000010
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#define BIT_5 0x00000020
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#define BIT_6 0x00000040
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#define BIT_7 0x00000080
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#define BIT_8 0x00000100
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#define BIT_9 0x00000200
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#define BIT_10 0x00000400
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#define BIT_11 0x00000800
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#define BIT_12 0x00001000
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#define BIT_13 0x00002000
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#define BIT_14 0x00004000
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#define BIT_15 0x00008000
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#define BIT_16 0x00010000
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#define BIT_17 0x00020000
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#define BIT_18 0x00040000
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#define BIT_19 0x00080000
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#define BIT_20 0x00100000
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#define BIT_21 0x00200000
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#define BIT_22 0x00400000
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#define BIT_23 0x00800000
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#define BIT_24 0x01000000
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#define BIT_25 0x02000000
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#define BIT_26 0x04000000
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#define BIT_27 0x08000000
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#define BIT_28 0x10000000
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#define BIT_29 0x20000000
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#define BIT_30 0x40000000
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#define BIT_31 0x80000000
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/*------------------------------------------------------------------------------*/
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/* I/O Processor Register Map */
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/*------------------------------------------------------------------------------*/
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#define SYSCON 0x00
/* System configuration register */
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#define VIRPT 0x01
/* Vector interrupt register */
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#define WAIT 0x02
/* External Port Wait register - renamed to EPCON */
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#define EPCON 0x02
/* External Port configuration register */
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#define SYSTAT 0x03
/* System status register */
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/* the upper 32-bits of the 64-bit epbxs are only accessible as 64-bit reference*/
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#define EPB0 0x04
/* External port DMA buffer 0 */
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#define EPB1 0x06
/* External port DMA buffer 1 */
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#define MSGR0 0x08
/* Message register 0 */
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#define MSGR1 0x09
/* Message register 1 */
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#define MSGR2 0x0a
/* Message register 2 */
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#define MSGR3 0x0b
/* Message register 3 */
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#define MSGR4 0x0c
/* Message register 4 */
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#define MSGR5 0x0d
/* Message register 5 */
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#define MSGR6 0x0e
/* Message register 6 */
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#define MSGR7 0x0f
/* Message register 7 */
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/* IOP shadow registers of the core control regs */
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#define PC_SHDW 0x10
/* PC IOP shadow register (PC[23-0]) */
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#define MODE2_SHDW 0x11
/* Mode2 IOP shadow register (MODE2[31-25]) */
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#define EPB2 0x14
/* EXternal port DMA buffer 2 */
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#define EPB3 0x16
/* External port DMA buffer 3 */
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#define BMAX 0x18
/* Bus time-out maximum */
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#define BCNT 0x19
/* Bus time-out counter */
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#define ELAST 0x1b
/* Address of last external access for page detect */
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#define DMAC10 0x1c
/* EP DMA10 control register */
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#define DMAC11 0x1d
/* EP DMA11 control register */
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#define DMAC12 0x1e
/* EP DMA12 control register */
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#define DMAC13 0x1f
/* EP DMA13 Control register */
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#define II4 0x30
/* Internal DMA4 memory address */
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#define IM4 0x31
/* Internal DMA4 memory access modifier */
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#define C4 0x32
/* Contains number of DMA4 transfers remaining */
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#define CP4 0x33
/* Points to next DMA4 parameters */
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#define GP4 0x34
/* DMA4 General purpose / 2-D DMA */
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#define DB4 0x35
/* DMA4 General purpose / 2-D DMA */
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#define DA4 0x36
/* DMA4 General purpose / 2-D DMA */
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/* DMA Channel 4 Corresponds to LBUF 0 */
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#define IILB0 0x30
/* Internal DMA4 memory address */
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#define IMLB0 0x31
/* Internal DMA4 memory access modifier */
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#define CLB0 0x32
/* Contains number of DMA4 transfers remaining */
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#define CPLB0 0x33
/* Points to next DMA4 parameters */
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#define GPLB0 0x34
/* DMA4 General purpose / 2-D DMA */
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#define DBLB0 0x35
/* DMA4 General purpose / 2-D DMA */
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#define DALB0 0x36
/* DMA4 General purpose / 2-D DMA */
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#define DMASTAT 0x37
/* DMA channel status register */
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#define II5 0x38
/* Internal DMA5 memory address */
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#define IM5 0x39
/* Internal DMA5 memory access modifier */
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#define C5 0x3a
/* Contains number of DMA5 transfers remainnig */
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#define CP5 0x3b
/* Points to next DMA5 parameters */
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#define GP5 0x3c
/* DMA5 General purpose / 2-D DMA */
128
#define DB5 0x3d
/* DMA5 General pu rpose / 2-D DMA */
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#define DA5 0x3e
/* DMA5 General purpose / 2-D DMA */
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131
/* DMA Channel 5 Corresponds to LBUF 1 */
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#define IILB1 0x38
/* Internal DMA5 memory address */
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#define IMLB1 0x39
/* Internal DMA5 memory access modifier */
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#define CLB1 0x3a
/* Contains number of DMA5 transfers remainnig */
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#define CPLB1 0x3b
/* Points to next DMA5 parameters */
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#define GPLB1 0x3c
/* DMA5 General purpose / 2-D DMA */
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#define DBLB1 0x3d
/* DMA5 General pu rpose / 2-D DMA */
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#define DALB1 0x3e
/* DMA5 General purpose / 2-D DMA */
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#define II10 0x40
/* Internal DMA10 memory address */
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#define IM10 0x41
/* Internal DMA10 memory access modifier */
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#define C10 0x42
/* Contains number of DMA10 transfers remainnig */
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#define CP10 0x43
/* Points to next DMA10 parameters */
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#define GP10 0x44
/* DMA10 General purpose */
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#define EI10 0x45
/* External DMA10 address */
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#define EM10 0x46
/* External DMA10 address modifier */
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#define EC10 0x47
/* External DMA10 counter */
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149
/* DMA Channel 10 Corresponds to EPB 0 */
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#define IIEP0 0x40
/* Internal DMA10 memory address */
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#define IMEP0 0x41
/* Internal DMA10 memory access modifier */
152
#define CEP0 0x42
/* Contains number of DMA10 transfers remainnig */
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#define CPEP0 0x43
/* Points to next DMA10 parameters */
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#define GPEP0 0x44
/* DMA10 General purpose */
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#define EIEP0 0x45
/* External DMA10 address */
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#define EMEP0 0x46
/* External DMA10 address modifier */
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#define ECEP0 0x47
/* External DMA10 counter */
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159
#define II11 0x48
/* Internal DMA11 memory address */
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#define IM11 0x49
/* Internal DMA11 memory access modifier */
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#define C11 0x4a
/* Contains number of DMA11 transfers remainnig */
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#define CP11 0x4b
/* Points to next DMA11 parameters */
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#define GP11 0x4c
/* DMA11 General purpose */
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#define EI11 0x4d
/* External DMA11 address */
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#define EM11 0x4e
/* External DMA11 address modifier */
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#define EC11 0x4f
/* External DMA counter */
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168
/* DMA Channel 11 Corresponds to EPB 1 */
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#define IIEP1 0x48
/* Internal DMA11 memory address */
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#define IMEP1 0x49
/* Internal DMA11 memory access modifier */
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#define CEP1 0x4a
/* Contains number of DMA11 transfers remainnig */
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#define CPEP1 0x4b
/* Points to next DMA11 parameters */
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#define GPEP1 0x4c
/* DMA11 General purpose */
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#define EIEP1 0x4d
/* External DMA11 address */
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#define EMEP1 0x4e
/* External DMA11 address modifier */
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#define ECEP1 0x4f
/* External DMA counter */
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#define II12 0x50
/* Internal DMA12 memory address */
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#define IM12 0x51
/* Internal DMA12 memory access modifier */
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#define C12 0x52
/* Contains number of DMA12 transfers remainnig */
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#define CP12 0x53
/* Points to next DMA12 parameters */
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#define GP12 0x54
/* DMA12 General purpose */
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#define EI12 0x55
/* External DMA12 address */
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#define EM12 0x56
/* External DMA12 address modifier */
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#define EC12 0x57
/* External DMA12 counter */
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/* DMA Channel 12 Corresponds to EPB 2 */
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#define IIEP2 0x50
/* Internal DMA12 memory address */
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#define IMEP2 0x51
/* Internal DMA12 memory access modifier */
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#define CEP2 0x52
/* Contains number of DMA12 transfers remainnig */
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#define CPEP2 0x53
/* Points to next DMA12 parameters */
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#define GPEP2 0x54
/* DMA12 General purpose */
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#define EIEP2 0x55
/* External DMA12 address */
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#define EMEP2 0x56
/* External DMA12 address modifier */
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#define ECEP2 0x57
/* External DMA12 counter */
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#define II13 0x58
/* Internal DMA13 memory address */
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#define IM13 0x59
/* Internal DMA13 memory access modifier */
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#define C13 0x5a
/* Contains number of DMA13 transfers remainnig */
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#define CP13 0x5b
/* Points to next DMA13 parameters */
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#define GP13 0x5c
/* DMA13 General purpose */
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#define EI13 0x5d
/* External DMA13 address */
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#define EM13 0x5e
/* External DMA13 address modifier */
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#define EC13 0x5f
/* External DMA13 counter */
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/* DMA Channel 13 Corresponds to EPB 3 */
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#define IIEP3 0x58
/* Internal DMA13 memory address */
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#define IMEP3 0x59
/* Internal DMA13 memory access modifier */
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#define CEP3 0x5a
/* Contains number of DMA13 transfers remainnig */
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#define CPEP3 0x5b
/* Points to next DMA13 parameters */
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#define GPEP3 0x5c
/* DMA13 General purpose */
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#define EIEP3 0x5d
/* External DMA13 address */
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#define EMEP3 0x5e
/* External DMA13 address modifier */
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#define ECEP3 0x5f
/* External DMA13 counter */
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#define II0 0x60
/* Internal DMA0 memory address */
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#define IM0 0x61
/* Internal DMA0 memory access modifier */
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#define C0 0x62
/* Contains number of DMA0 transfers remainnig */
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#define CP0 0x63
/* Points to next DMA0 parameters */
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#define GP0 0x64
/* DMA0 General purpose / 2-D DMA */
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#define DB0 0x65
/* DMA0 General purpose / 2-D DMA */
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#define DA0 0x66
/* DMA0 General purpose / 2-D DMA */
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/* DMA Channel 0 Corresponds to SPORT 0 RX */
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#define IIRX0 0x60
/* Internal DMA0 memory address */
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#define IMRX0 0x61
/* Internal DMA0 memory access modifier */
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#define CRX0 0x62
/* Contains number of DMA0 transfers remainnig */
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#define CPRX0 0x63
/* Points to next DMA0 parameters */
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#define GPRX0 0x64
/* DMA0 General purpose / 2-D DMA */
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#define DBRX0 0x65
/* DMA0 General purpose / 2-D DMA */
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#define DARX0 0x66
/* DMA0 General purpose / 2-D DMA */
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#define II1 0x68
/* Internal DMA1 memory address */
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#define IM1 0x69
/* Internal DMA1 memory access modifier */
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#define C1 0x6a
/* Contains number of DMA1 transfers remainnig */
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#define CP1 0x6b
/* Points to next DMA1 parameters */
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#define GP1 0x6c
/* DMA1 General purpose / 2-D DMA */
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#define DB1 0x6d
/* DMA1 General purpose / 2-D DMA */
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#define DA1 0x6e
/* DMA1 General purpose / 2-D DMA */
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/* DMA Channel 1 Corresponds to SPORT 1 RX */
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#define IIRX1 0x68
/* Internal DMA1 memory address */
243
#define IMRX1 0x69
/* Internal DMA1 memory access modifier */
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#define CRX1 0x6a
/* Contains number of DMA1 transfers remainnig */
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#define CPRX1 0x6b
/* Points to next DMA1 parameters */
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#define GPRX1 0x6c
/* DMA1 General purpose / 2-D DMA */
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#define DBRX1 0x6d
/* DMA1 General purpose / 2-D DMA */
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#define DARX1 0x6e
/* DMA1 General purpose / 2-D DMA */
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#define II2 0x70
/* Internal DMA2 memory address */
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#define IM2 0x71
/* Internal DMA2 memory access modifier */
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#define C2 0x72
/* Contains number of DMA2 transfers remainnig */
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#define CP2 0x73
/* Points to next DMA2 parameters */
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#define GP2 0x74
/* DMA2 General purpose / 2-D DMA */
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#define DB2 0x75
/* DMA2 General purpose / 2-D DMA */
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#define DA2 0x76
/* DMA2 General purpose / 2-D DMA */
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258
/* DMA Channel 2 Corresponds to SPORT 0 TX */
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#define IITX0 0x70
/* Internal DMA2 memory address */
260
#define IMTX0 0x71
/* Internal DMA2 memory access modifier */
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#define CTX0 0x72
/* Contains number of DMA2 transfers remainnig */
262
#define CPTX0 0x73
/* Points to next DMA2 parameters */
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#define GPTX0 0x74
/* DMA2 General purpose / 2-D DMA */
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#define DBTX0 0x75
/* DMA2 General purpose / 2-D DMA */
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#define DATX0 0x76
/* DMA2 General purpose / 2-D DMA */
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#define II3 0x78
/* Internal DMA3 memory address */
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#define IM3 0x79
/* Internal DMA3 memory access modifier */
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#define C3 0x7a
/* Contains number of DMA3 transfers remainnig */
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#define CP3 0x7b
/* Points to next DMA3 parameters */
271
#define GP3 0x7c
/* DMA3 General purpose / 2-D DMA */
272
#define DB3 0x7d
/* DMA3 General purpose / 2-D DMA */
273
#define DA3 0x7e
/* DMA3 General purpose / 2-D DMA */
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275
/* DMA Channel 3 Corresponds to SPORT 1 TX */
276
#define IITX1 0x78
/* Internal DMA3 memory address */
277
#define IMTX1 0x79
/* Internal DMA3 memory access modifier */
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#define CTX1 0x7a
/* Contains number of DMA3 transfers remainnig */
279
#define CPTX1 0x7b
/* Points to next DMA3 parameters */
280
#define GPTX1 0x7c
/* DMA3 General purpose / 2-D DMA */
281
#define DBTX1 0x7d
/* DMA3 General purpose / 2-D DMA */
282
#define DATX1 0x7e
/* DMA3 General purpose / 2-D DMA */
283
284
#define II6 0x80
/* Internal DMA6 memory address */
285
#define IM6 0x81
/* Internal DMA6 memory access modifier */
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#define C6 0x82
/* Contains number of DMA6 transfers remainnig */
287
#define CP6 0x83
/* Points to next DMA6 parameters */
288
#define GP6 0x84
/* DMA6 General purpose / 2-D DMA */
289
#define DB6 0x85
/* DMA6 General purpose / 2-D DMA */
290
#define DA6 0x86
/* DMA6 General purpose / 2-D DMA */
291
292
/* DMA Channel 6 Corresponds to LBUF 2 */
293
#define IILB2 0x80
/* Internal DMA6 memory address */
294
#define IMLB2 0x81
/* Internal DMA6 memory access modifier */
295
#define CLB2 0x82
/* Contains number of DMA6 transfers remainnig */
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#define CPLB2 0x83
/* Points to next DMA6 parameters */
297
#define GPLB2 0x84
/* DMA6 General purpose / 2-D DMA */
298
#define DBLB2 0x85
/* DMA6 General purpose / 2-D DMA */
299
#define DALB2 0x86
/* DMA6 General purpose / 2-D DMA */
300
301
#define II7 0x88
/* Internal DMA7 memory address */
302
#define IM7 0x89
/* Internal DMA7 memory access modifier */
303
#define C7 0x8a
/* Contains number of DMA7 transfers remainnig */
304
#define CP7 0x8b
/* Points to next DMA7 parameters */
305
#define GP7 0x8c
/* DMA7 General purpose / 2-D DMA */
306
#define DB7 0x8d
/* DMA7 General purpose / 2-D DMA */
307
#define DA7 0x8e
/* DMA7 General purpose / 2-D DMA */
308
309
/* DMA Channel 7 Corresponds to LBUF 3 */
310
#define IILB3 0x88
/* Internal DMA7 memory address */
311
#define IMLB3 0x89
/* Internal DMA7 memory access modifier */
312
#define CLB3 0x8a
/* Contains number of DMA7 transfers remainnig */
313
#define CPLB3 0x8b
/* Points to next DMA7 parameters */
314
#define GPLB3 0x8c
/* DMA7 General purpose / 2-D DMA */
315
#define DBLB3 0x8d
/* DMA7 General purpose / 2-D DMA */
316
#define DALB3 0x8e
/* DMA7 General purpose / 2-D DMA */
317
318
#define II8 0x90
/* Internal DMA8 memory address */
319
#define IM8 0x91
/* Internal DMA8 memory access modifier */
320
#define C8 0x92
/* Contains number of DMA8 transfers remainnig */
321
#define CP8 0x93
/* Points to next DMA8 parameters */
322
#define GP8 0x94
/* DMA8 General purpose / 2-D DMA */
323
#define DB8 0x95
/* DMA8 General purpose / 2-D DMA */
324
#define DA8 0x96
/* DMA8 General purpose / 2-D DMA */
325
326
/* DMA Channel 8 Corresponds to LBUF 4 */
327
#define IILB4 0x90
/* Internal DMA8 memory address */
328
#define IMLB4 0x91
/* Internal DMA8 memory access modifier */
329
#define CLB4 0x92
/* Contains number of DMA8 transfers remainnig */
330
#define CPLB4 0x93
/* Points to next DMA8 parameters */
331
#define GPLB4 0x94
/* DMA8 General purpose / 2-D DMA */
332
#define DBLB4 0x95
/* DMA8 General purpose / 2-D DMA */
333
#define DALB4 0x96
/* DMA8 General purpose / 2-D DMA */
334
335
#define II9 0x98
/* Internal DMA9 memory address */
336
#define IM9 0x99
/* Internal DMA9 memory access modifier */
337
#define C9 0x9a
/* Contains number of DMA9 transfers remainnig */
338
#define CP9 0x9b
/* Points to next DMA9 parameters */
339
#define GP9 0x9c
/* DMA9 General purpose / 2-D DMA */
340
#define DB9 0x9d
/* DMA9 General purpose / 2-D DMA */
341
#define DA9 0x9e
/* DMA9 General purpose / 2-D DMA */
342
343
/* DMA Channel 9 Corresponds to LBUF 5 */
344
#define IILB5 0x98
/* Internal DMA9 memory address */
345
#define IMLB5 0x99
/* Internal DMA9 memory access modifier */
346
#define CLB5 0x9a
/* Contains number of DMA9 transfers remainnig */
347
#define CPLB5 0x9b
/* Points to next DMA9 parameters */
348
#define GPLB5 0x9c
/* DMA9 General purpose / 2-D DMA */
349
#define DBLB5 0x9d
/* DMA9 General purpose / 2-D DMA */
350
#define DALB5 0x9e
/* DMA9 General purpose / 2-D DMA */
351
352
/* Emulation/Breakpoint Registers (remapped from UREG space) */
353
/* NOTES:
354
- These registers are ONLY accessible by the core
355
- It is *highly* recommended that these facilities be accessed only
356
through the ADI emulator routines
357
*/
358
/* Core Emulation HWBD Registers */
359
#define PSA1S 0xa0
/* Instruction address start #1 */
360
#define PSA1E 0xa1
/* Instruction address end #1 */
361
#define PSA2S 0xa2
/* Instruction address start #2 */
362
#define PSA2E 0xa3
/* Instruction address end #2 */
363
#define PSA3S 0xa4
/* Instruction address start #3 */
364
#define PSA3E 0xa5
/* Instruction address end #3 */
365
#define PSA4S 0xa6
/* Instruction address start #4 */
366
#define PSA4E 0xa7
/* Instruction address end #4 */
367
#define PMDAS 0xa8
/* Program Data address start */
368
#define PMDAE 0xa9
/* Program Data address end */
369
#define DMA1S 0xaa
/* Data address start #1 */
370
#define DMA1E 0xab
/* Data address end #1 */
371
#define DMA2S 0xac
/* Data address start #2 */
372
#define DMA2E 0xad
/* Data address end #2 */
373
#define EMUN 0xae
/* hwbp hit-count register */
374
375
/* IOP Emulation HWBP Bounds Registers */
376
#define IOAS 0xb0
/* IOA Upper Bounds Register */
377
#define IOAE 0xb1
/* IOA Lower Bounds Register */
378
#define EPAS 0xb2
/* EPA Upper Bounds Register */
379
#define EPAE 0xb3
/* EPA Lower Bounds Register */
380
381
#define LBUF0 0xc0
/* Link buffer 0 */
382
#define LBUF1 0xc2
/* Link buffer 1 */
383
#define LBUF2 0xc4
/* Link buffer 2 */
384
#define LBUF3 0xc6
/* Link buffer 3 */
385
#define LBUF4 0xc8
/* Link buffer 4 */
386
#define LBUF5 0xca
/* Link buffer 5 */
387
#define LCTL0 0xcc
/* Link buffer control */
388
#define LCTL1 0xcd
/* Link buffer control */
389
#define LCOM 0xce
/* Link common control */
390
#define LAR 0xcf
/* Link assignment register */
391
#define LSRQ 0xd0
/* Link service request and mask register */
392
#define LPATH1 0xd1
/* Link path register 1 */
393
#define LPATH2 0xd2
/* Link path register 2 */
394
#define LPATH3 0xd3
/* Link path register 3 */
395
#define LPCNT 0xd4
/* Link path counter */
396
#define CNST1 0xd5
/* Link port constant 1 register */
397
#define CNST2 0xd6
/* Link port constant 2 register */
398
399
#define STCTL0 0xe0
/* Serial Port 0 Transmit Control Register */
400
#define SRCTL0 0xe1
/* Serial Port 0 Receive Control Register */
401
#define TX0 0xe2
/* Serial Port 0 Transmit Data Buffer */
402
#define RX0 0xe3
/* Serial Port 0 Receive Data Buffer */
403
#define TDIV0 0xe4
/* Serial Port 0 Transmit Divisor */
404
#define TCNT0 0xe5
/* Serial Port 0 Transmit Count Reg */
405
#define RDIV0 0xe6
/* Serial Port 0 Receive Divisor */
406
#define RCNT0 0xe7
/* Serial Port 0 Receive Count Reg */
407
#define MTCS0 0xe8
/* Serial Port 0 Mulitchannel Transmit Selector */
408
#define MRCS0 0xe9
/* Serial Port 0 Mulitchannel Receive Selector */
409
#define MTCCS0 0xea
/* Serial Port 0 Mulitchannel Transmit Selector */
410
#define MRCCS0 0xeb
/* Serial Port 0 Mulitchannel Receive Selector */
411
#define KEYWD0 0xec
/* Serial Port 0 Receive Comparison Register */
412
#define KEYMASK0 0xed
/* Serial Port 0 Receive Comparison Mask Register */
413
#define SPATH0 0xee
/* Serial Port 0 Path Length (Mesh Multiprocessing) */
414
#define SPCNT0 0xef
/* Serial Port 0 Path Counter (Mesh Multiprocessing) */
415
416
#define STCTL1 0xf0
/* Serial Port 1 Transmit Control Register */
417
#define SRCTL1 0xf1
/* Serial Port 1 Receive Control Register */
418
#define TX1 0xf2
/* Serial Port 1 Transmit Data Buffer */
419
#define RX1 0xf3
/* Serial Port 1 Receive Data Buffer */
420
#define TDIV1 0xf4
/* Serial Port 1 Transmit Divisor */
421
#define TCNT1 0xf5
/* Serial Port 1 Transmit Count Reg */
422
#define RDIV1 0xf6
/* Serial Port 1 Receive Divisor */
423
#define RCNT1 0xf7
/* Serial Port 1 Receive Count Reg */
424
#define MTCS1 0xf8
/* Serial Port 1 Mulitchannel Transmit Selector */
425
#define MRCS1 0xf9
/* Serial Port 1 Mulitchannel Receive Selector */
426
#define MTCCS1 0xfa
/* Serial Port 1 Mulitchannel Transmit Selector */
427
#define MRCCS1 0xfb
/* Serial Port 1 Mulitchannel Receive Selector */
428
#define KEYWD1 0xfc
/* Serial Port 1 Receive Comparison Register */
429
#define KEYMASK1 0xfd
/* Serial Port 1 Receive Comparison Mask Register */
430
#define SPATH1 0xfe
/* Serial Port 1 Path Length (Mesh Multiprocessing) */
431
#define SPCNT1 0xff
/* Serial Port 1 Path Counter (Mesh Multiprocessing) */
432
433
434
/*------------------------------------------------------------------------------*/
435
/* System Register bit definitions */
436
/*------------------------------------------------------------------------------*/
437
/* MODE1 and MMASK registers */
438
#define BR8 BIT_0
/* Bit 0: Bit-reverse for I8 */
439
#define BR0 BIT_1
/* Bit 1: Bit-reverse for I0 (uses DMS0- only ) */
440
#define SRCU BIT_2
/* Bit 2: Alt. register select for comp. units */
441
#define SRD1H BIT_3
/* Bit 3: DAG1 alt. register select (7-4) */
442
#define SRD1L BIT_4
/* Bit 4: DAG1 alt. register select (3-0) */
443
#define SRD2H BIT_5
/* Bit 5: DAG2 alt. register select (15-12) */
444
#define SRD2L BIT_6
/* Bit 6: DAG2 alt. register select (11-8) */
445
#define SRRFH BIT_7
/* Bit 7: Register file alt. select for R(15-8) */
446
#define SRRFL BIT_10
/* Bit 10: Register file alt. select for R(7-0) */
447
#define NESTM BIT_11
/* Bit 11: Interrupt nesting enable */
448
#define IRPTEN BIT_12
/* Bit 12: Global interrupt enable */
449
#define ALUSAT BIT_13
/* Bit 13: Enable ALU fixed-pt. saturation */
450
#define SSE BIT_14
/* Bit 14: Enable short word sign extension */
451
#define TRUNCATE BIT_15
/* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest */
452
#define RND32 BIT_16
/* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd */
453
#define CSEL (BIT_17|BIT_18)
/* Bit 17-18: CSelect: Bus Mastership */
454
#define PEYEN BIT_21
/* Bit 21: Processing Element Y enable */
455
#define SIMD BIT_21
/* Bit 21: Enable SIMD Mode */
456
#define BDCST9 BIT_22
/* Bit 22: Load Broadcast for I9 */
457
#define BDCST1 BIT_23
/* Bit 23: Load Broadcast for I1 */
458
#define CBUFEN BIT_24
/* Bit 23: Circular Buffer Enable */
459
460
/* MODE2 register */
461
#define IRQ0E BIT_0
/* Bit 0: IRQ0- 1=edge sens. 0=level sens. */
462
#define IRQ1E BIT_1
/* Bit 1: IRQ1- 1=edge sens. 0=level sens. */
463
#define IRQ2E BIT_2
/* Bit 2: IRQ2- 1=edge sens. 0=level sens. */
464
#define CADIS BIT_4
/* Bit 4: Cache disable */
465
#define TIMEN BIT_5
/* Bit 5: Timer enable */
466
#define BUSLK BIT_6
/* Bit 6: External bus lock */
467
#define FLG0O BIT_15
/* Bit 15: FLAG0 1=output 0=input */
468
#define FLG1O BIT_16
/* Bit 16: FLAG1 1=output 0=input */
469
#define FLG2O BIT_17
/* Bit 17: FLAG2 1=output 0=input */
470
#define FLG3O BIT_18
/* Bit 18: FLAG3 1=output 0=input */
471
#define CAFRZ BIT_19
/* Bit 19: Cache freeze */
472
#define IIRAE BIT_20
/* Bit 20: Illegal IOP Register Access Enable */
473
#define U64MAE BIT_21
/* Bit 21: Unaligned 64-bit Memory Access Enable */
474
/* bits 31-30, 27-25 are Processor Type[4:0], read only, value: 0b01001
475
bits 29-28 are silicon revision[1:0], read only, value: 0
476
477
These bits (only) are routed to Mode2 Shadow register (IOP register ox11)
478
*/
479
480
/* FLAGS register */
481
#define FLG0 BIT_0
/* Bit 0: FLAG0 value */
482
#define FLG1 BIT_1
/* Bit 1: FLAG1 value */
483
#define FLG2 BIT_2
/* Bit 2: FLAG2 value */
484
#define FLG3 BIT_3
/* Bit 3: FLAG3 value */
485
486
/* ASTATx and ASTATy registers */
487
#ifdef SUPPORT_DEPRECATED_USAGE
488
/* Several of these (AV, AC, MV, SV, SZ) are assembler-reserved keywords,
489
so this style is now deprecated. If these are defined, the assembler-
490
reserved keywords are still available in lowercase, e.g.,
491
IF sz JUMP LABEL1.
492
*/
493
# define AZ BIT_0
/* Bit 0: ALU result zero or fltg-pt. underflow */
494
# define AV BIT_1
/* Bit 1: ALU overflow */
495
# define AN BIT_2
/* Bit 2: ALU result negative */
496
# define AC BIT_3
/* Bit 3: ALU fixed-pt. carry */
497
# define AS BIT_4
/* Bit 4: ALU X input sign (ABS and MANT ops) */
498
# define AI BIT_5
/* Bit 5: ALU fltg-pt. invalid operation */
499
# define MN BIT_6
/* Bit 6: Multiplier result negative */
500
# define MV BIT_7
/* Bit 7: Multiplier overflow */
501
# define MU BIT_8
/* Bit 8: Multiplier fltg-pt. underflow */
502
# define MI BIT_9
/* Bit 9: Multiplier fltg-pt. invalid operation */
503
# define AF BIT_10
/* Bit 10: ALU fltg-pt. operation */
504
# define SV BIT_11
/* Bit 11: Shifter overflow */
505
# define SZ BIT_12
/* Bit 12: Shifter result zero */
506
# define SS BIT_13
/* Bit 13: Shifter input sign */
507
# define BTF BIT_18
/* Bit 18: Bit test flag for system registers */
508
# define CACC0 BIT_24
/* Bit 24: Compare Accumulation Bit 0 */
509
# define CACC1 BIT_25
/* Bit 25: Compare Accumulation Bit 1 */
510
# define CACC2 BIT_26
/* Bit 26: Compare Accumulation Bit 2 */
511
# define CACC3 BIT_27
/* Bit 27: Compare Accumulation Bit 3 */
512
# define CACC4 BIT_28
/* Bit 28: Compare Accumulation Bit 4 */
513
# define CACC5 BIT_29
/* Bit 29: Compare Accumulation Bit 5 */
514
# define CACC6 BIT_30
/* Bit 30: Compare Accumulation Bit 6 */
515
# define CACC7 BIT_31
/* Bit 31: Compare Accumulation Bit 7 */
516
517
#endif
518
519
#define ASTAT_AZ BIT_0
/* Bit 0: ALU result zero or fltg-pt. u'flow*/
520
#define ASTAT_AV BIT_1
/* Bit 1: ALU overflow */
521
#define ASTAT_AN BIT_2
/* Bit 2: ALU result negative */
522
#define ASTAT_AC BIT_3
/* Bit 3: ALU fixed-pt. carry */
523
#define ASTAT_AS BIT_4
/* Bit 4: ALU X input sign(ABS and MANT ops)*/
524
#define ASTAT_AI BIT_5
/* Bit 5: ALU fltg-pt. invalid operation */
525
#define ASTAT_MN BIT_6
/* Bit 6: Multiplier result negative */
526
#define ASTAT_MV BIT_7
/* Bit 7: Multiplier overflow */
527
#define ASTAT_MU BIT_8
/* Bit 8: Multiplier fltg-pt. underflow */
528
#define ASTAT_MI BIT_9
/* Bit 9: Multiplier fltg-pt. invalid op. */
529
#define ASTAT_AF BIT_10
/* Bit 10: ALU fltg-pt. operation */
530
#define ASTAT_SV BIT_11
/* Bit 11: Shifter overflow */
531
#define ASTAT_SZ BIT_12
/* Bit 12: Shifter result zero */
532
#define ASTAT_SS BIT_13
/* Bit 13: Shifter input sign */
533
#define ASTAT_BTF BIT_18
/* Bit 18: Bit test flag for system registers*/
534
#define ASTAT_CACC0 BIT_24
/* Bit 24: Compare Accumulation Bit 0 */
535
#define ASTAT_CACC1 BIT_25
/* Bit 25: Compare Accumulation Bit 1 */
536
#define ASTAT_CACC2 BIT_26
/* Bit 26: Compare Accumulation Bit 2 */
537
#define ASTAT_CACC3 BIT_27
/* Bit 27: Compare Accumulation Bit 3 */
538
#define ASTAT_CACC4 BIT_28
/* Bit 28: Compare Accumulation Bit 4 */
539
#define ASTAT_CACC5 BIT_29
/* Bit 29: Compare Accumulation Bit 5 */
540
#define ASTAT_CACC6 BIT_30
/* Bit 30: Compare Accumulation Bit 6 */
541
#define ASTAT_CACC7 BIT_31
/* Bit 31: Compare Accumulation Bit 7 */
542
543
/* STKYx and STKYy registers */
544
#define AUS BIT_0
/* Bit 0: ALU fltg-pt. underflow */
545
#define AVS BIT_1
/* Bit 1: ALU fltg-pt. overflow */
546
#define AOS BIT_2
/* Bit 2: ALU fixed-pt. overflow */
547
#define AIS BIT_5
/* Bit 5: ALU fltg-pt. invalid operation */
548
#define MOS BIT_6
/* Bit 6: Multiplier fixed-pt. overflow */
549
#define MVS BIT_7
/* Bit 7: Multiplier fltg-pt. overflow */
550
#define MUS BIT_8
/* Bit 8: Multiplier fltg-pt. underflow */
551
#define MIS BIT_9
/* Bit 9: Multiplier fltg-pt. invalid operation */
552
#define CB7S BIT_17
/* Bit 17: DAG1 circular buffer 7 overflow */
553
#define CB15S BIT_18
/* Bit 18: DAG2 circular buffer 15 overflow */
554
#define PCFL BIT_21
/* Bit 21: PC stack full */
555
#define PCEM BIT_22
/* Bit 22: PC stack empty */
556
#define SSOV BIT_23
/* Bit 23: Status stack overflow (MODE1 and ASTAT) */
557
#define SSEM BIT_24
/* Bit 24: Status stack empty */
558
#define LSOV BIT_25
/* Bit 25: Loop stack overflow */
559
#define LSEM BIT_26
/* Bit 26: Loop stack empty */
560
561
/* STKYx register *ONLY* */
562
#define IIRA BIT_19
/* Bit 19: Illegal IOP Register Access */
563
#define U64MA BIT_20
/* Bit 20: Unaligned 64-bit Memory Access */
564
565
/* IRPTL and IMASK and IMASKP registers */
566
#define EMUI BIT_0
/* Bit 0: Offset: 00: Emulator Interrupt */
567
#define RSTI BIT_1
/* Bit 1: Offset: 04: Reset */
568
#define IICDI BIT_2
/* Bit 2: Offset: 08: Illegal Input Condition Detected */
569
#define SOVFI BIT_3
/* Bit 3: Offset: 0c: Stack overflow */
570
#define TMZHI BIT_4
/* Bit 4: Offset: 10: Timer = 0 (high priority) */
571
#define VIRPTI BIT_5
/* Bit 5: Offset: 14: Vector interrupt */
572
#define IRQ2I BIT_6
/* Bit 6: Offset: 18: IRQ2- asserted */
573
#define IRQ1I BIT_7
/* Bit 7: Offset: 1c: IRQ1- asserted */
574
#define IRQ0I BIT_8
/* Bit 8: Offset: 20: IRQ0- asserted */
575
#define SPR0I BIT_10
/* Bit 10: Offset: 28: SPORT0 receive DMA channel */
576
#define SPR1I BIT_11
/* Bit 11: Offset: 2c: SPORT1 receive DMA channel */
577
#define SPT0I BIT_12
/* Bit 12: Offset: 30: SPORT0 transmit DMA channel */
578
#define SPT1I BIT_13
/* Bit 13: Offset: 34: SPORT1 transmit DMA channel */
579
#define LPISUMI BIT_14
/* Bit 14: Offset: na: LPort Interrupt Summary */
580
#define EP0I BIT_15
/* Bit 15: Offset: 50: External port channel 0 DMA */
581
#define EP1I BIT_16
/* Bit 16: Offset: 54: External port channel 1 DMA */
582
#define EP2I BIT_17
/* Bit 17: Offset: 58: External port channel 2 DMA */
583
#define EP3I BIT_18
/* Bit 18: Offset: 5c: External port channel 3 DMA */
584
#define LSRQI BIT_19
/* Bit 19: Offset: 60: Link service request */
585
#define CB7I BIT_20
/* Bit 20: Offset: 64: Circ. buffer 7 overflow */
586
#define CB15I BIT_21
/* Bit 21: Offset: 68: Circ. buffer 15 overflow */
587
#define TMZLI BIT_22
/* Bit 22: Offset: 6c: Timer = 0 (low priority) */
588
#define FIXI BIT_23
/* Bit 23: Offset: 70: Fixed-pt. overflow */
589
#define FLTOI BIT_24
/* Bit 24: Offset: 74: fltg-pt. overflow */
590
#define FLTUI BIT_25
/* Bit 25: Offset: 78: fltg-pt. underflow */
591
#define FLTII BIT_26
/* Bit 26: Offset: 7c: fltg-pt. invalid */
592
#define SFT0I BIT_27
/* Bit 27: Offset: 80: user software int 0 */
593
#define SFT1I BIT_28
/* Bit 28: Offset: 84: user software int 1 */
594
#define SFT2I BIT_29
/* Bit 39: Offset: 88: user software int 2 */
595
#define SFT3I BIT_30
/* Bit 30: Offset: 8c: user software int 3 */
596
597
/* LIRPTL register */
598
#define LP0I BIT_0
/* Bit 0: Offset: 38: Link port channel 0 DMA */
599
#define LP1I BIT_1
/* Bit 1: Offset: 3C: Link port channel 1 DMA */
600
#define LP2I BIT_2
/* Bit 2: Offset: 40: Link port channel 2 DMA */
601
#define LP3I BIT_3
/* Bit 3: Offset: 44: Link port channel 3 DMA */
602
#define LP4I BIT_4
/* Bit 4: Offset: 48: Link port channel 4 DMA */
603
#define LP5I BIT_5
/* Bit 5: Offset: 4C: Link port channel 5 DMA */
604
#define LP0MSK BIT_16
/* Bit 16: Link port channel 0 Interrupt Mask */
605
#define LP1MSK BIT_17
/* Bit 17: Link port channel 1 Interrupt Mask */
606
#define LP2MSK BIT_18
/* Bit 18: Link port channel 2 Interrupt Mask */
607
#define LP3MSK BIT_19
/* Bit 19: Link port channel 3 Interrupt Mask */
608
#define LP4MSK BIT_20
/* Bit 20: Link port channel 4 Interrupt Mask */
609
#define LP5MSK BIT_21
/* Bit 21: Link port channel 5 Interrupt Mask */
610
#define LP0MSKP BIT_24
/* Bit 24: Link port channel 0 Interrupt Mask Pointer*/
611
#define LP1MSKP BIT_25
/* Bit 25: Link port channel 1 Interrupt Mask Pointer*/
612
#define LP2MSKP BIT_26
/* Bit 26: Link port channel 2 Interrupt Mask Pointer*/
613
#define LP3MSKP BIT_27
/* Bit 27: Link port channel 3 Interrupt Mask Pointer*/
614
#define LP4MSKP BIT_28
/* Bit 28: Link port channel 4 Interrupt Mask Pointer*/
615
#define LP5MSKP BIT_29
/* Bit 29: Link port channel 5 Interrupt Mask Pointer*/
616
617
618
/*------------------------------------------------------------------------------*/
619
/* IOP Register Bit Definitions */
620
/*------------------------------------------------------------------------------*/
621
/* SYSCON Register */
622
#define SRST BIT_0
/* Soft Reset */
623
#define BSO BIT_1
/* Boot Select Override */
624
#define IIVT BIT_2
/* Internal Interrupt Vector Table */
625
#define IWT BIT_3
/* Instruction word transfer (0 = data, 1 = inst) */
626
#define HPM000 0x00000000
/* Host packing mode: None */
627
#define HPM001 BIT_4
/* Host packing mode: 16/48 */
628
#define HPM010 BIT_5
/* Host packing mode: 16/64 */
629
#define HPM011 (BIT_4|BIT_5)
/* Host packing mode: 32/48 */
630
#define HPM100 BIT_6
/* Host packing mode: 32/64 */
631
#define HMSWF BIT_7
/* Host packing order (0 = LSW first, 1 = MSW) */
632
#define HPFLSH BIT_8
/* Host pack flush */
633
#define IMDW0 BIT_9
/* Internal memory block 0, extended data (40 bit) */
634
#define IMDW1 BIT_10
/* Internal memory block 1, extended data (40 bit) */
635
#define ADREDY BIT_11
/* Active Drive Ready */
636
637
#define BHD BIT_16
/* Buffer Hand Disable */
638
#define EBPR00 0x00000000
/* External bus priority: Even */
639
#define EBPR01 BIT_17
/* External bus priority: Core has priority */
640
#define EBPR10 BIT_18
/* External bus priority: IO has priority */
641
642
#define DCPR BIT_19
/* Select rotating access priority on DMA10 - DMA13 */
643
#define LDCPR BIT_20
/* Select rotating access priority on DMA4 - DMA9 */
644
#define PRROT BIT_21
/* Select rotating prio between LPort and EPort */
645
#define COD BIT_22
/* Clock Out Disable */
646
647
#define IMGR BIT_28
/* Internal memory block grouping (for the MSP) */
648
649
/* SYSTAT Register */
650
#define HSTM BIT_0
/* Host is the Bus Master */
651
#define BSYN BIT_1
/* Bus arbitration logic is synchronized */
652
#define CRBM (BIT_4|BIT_5|BIT_6)
/* Current ADSP21160 Bus Master */
653
#define IDC (BIT_8|BIT_9|BIT_10)
/* ADSP21160 ID Code */
654
#define DWPD BIT_12
/* Direct write pending (0 = none, 1 = pending) */
655
#define VIPD BIT_13
/* Vector interrupt pending (1 = pending) */
656
#define HPS (BIT_14|BIT_15)
/* Host pack status */
657
#define CRAT (BIT_16|BIT_17|BIT_18)
/* CLK_CFG(3-0), Core:CLKIN clock ratio */
658
659
/* WAIT Register */
660
#define EB0AM1 BIT_0
/* Synchronous, writes are 0 wait state */
661
#define EB0AM2 BIT_1
/* Synchronous, writes are 1 wait state */
662
#define EB0WS1 BIT_2
/* 1 Waitstate, no hold time cycle */
663
#define EB0WS2 BIT_3
/* 2 Waitstates, hold time cycle */
664
#define EB0WS3 (BIT_2|BIT_3)
/* 3 Waitstates, hold time cycle */
665
#define EB0WS4 BIT_4
/* 4 Waitstates, hold time cycle */
666
#define EB0WS5 (BIT_2|BIT_4)
/* 5 Waitstates, hold time cycle */
667
#define EB0WS6 (BIT_3|BIT_4)
/* 6 Waitstates, hold time cycle */
668
#define EB0WS7 (BIT_2|BIT_3|BIT_4)
/* 7 Waitstates, hold time cycle */
669
#define EB1AM1 BIT_5
/* Synchronous, writes are 0 wait state */
670
#define EB1AM2 BIT_6
/* Synchronous, writes are 1 wait state */
671
#define EB1WS1 BIT_7
/* 1 Waitstate, no hold time cycle */
672
#define EB1WS2 BIT_8
/* 2 Waitstates, hold time cycle */
673
#define EB1WS3 (BIT_7|BIT_8)
/* 3 Waitstates, hold time cycle */
674
#define EB1WS4 BIT_9
/* 4 Waitstates, hold time cycle */
675
#define EB1WS5 (BIT_7|BIT_9)
/* 5 Waitstates, hold time cycle */
676
#define EB1WS6 (BIT_8|BIT_9)
/* 6 Waitstates, hold time cycle */
677
#define EB1WS7 (BIT_7|BIT_8|BIT_9)
/* 7 Waitstates, hold time cycle */
678
#define EB2AM1 BIT_10
/* Synchronous, writes are 0 wait state */
679
#define EB2AM2 BIT_11
/* Synchronous, writes are 1 wait state */
680
#define EB2WS1 BIT_12
/* 1 Waitstate, no hold time cycle */
681
#define EB2WS2 BIT_13
/* 2 Waitstates, hold time cycle */
682
#define EB2WS3 (BIT_12|BIT_13)
/* 3 Waitstates, hold time cycle */
683
#define EB2WS4 BIT_14
/* 4 Waitstates, hold time cycle */
684
#define EB2WS5 (BIT_12|BIT_14)
/* 5 Waitstates, hold time cycle */
685
#define EB2WS6 (BIT_13|BIT_14)
/* 6 Waitstates, hold time cycle */
686
#define EB2WS7 (BIT_12|BIT_13|BIT_14)
/* 7 Waitstates, hold time cycle */
687
#define EB3AM1 BIT_15
/* Synchronous, writes are 0 wait state */
688
#define EB3AM2 BIT_16
/* Synchronous, writes are 1 wait state */
689
#define EB3WS1 BIT_17
/* 1 Waitstate, no hold time cycle */
690
#define EB3WS2 BIT_18
/* 2 Waitstates, hold time cycle */
691
#define EB3WS3 (BIT_17|BIT_18)
/* 3 Waitstates, hold time cycle */
692
#define EB3WS4 BIT_19
/* 4 Waitstates, hold time cycle */
693
#define EB3WS5 (BIT_17|BIT_19)
/* 5 Waitstates, hold time cycle */
694
#define EB3WS6 (BIT_18|BIT_19)
/* 6 Waitstates, hold time cycle */
695
#define EB3WS7 (BIT_17|BIT_18|BIT_19)
/* 7 Waitstates, hold time cycle */
696
#define UBAM1 BIT_20
/* Synchronous, writes are 0 wait state */
697
#define UBAM2 BIT_21
/* Synchronous, writes are 1 wait state */
698
#define UBWS1 BIT_22
/* 1 Waitstate, no hold time cycle */
699
#define UBWS2 BIT_23
/* 2 Waitstates, hold time cycle */
700
#define UBWS3 (BIT_22|BIT_23)
/* 3 Waitstates, hold time cycle */
701
#define UBWS4 BIT_24
/* 4 Waitstates, hold time cycle */
702
#define UBWS5 (BIT_22|BIT_24)
/* 5 Waitstates, hold time cycle */
703
#define UBWS6 (BIT_23|BIT_24)
/* 6 Waitstates, hold time cycle */
704
#define UBWS7 (BIT_22|BIT_23|BIT_24)
/* 7 Waitstates, hold time cycle */
705
#define PAGSZ0 BIT_25
/* 512 word DRAM page size */
706
#define PAGSZ1 BIT_26
/* 1024 word (1K) DRAM page size */
707
#define PAGSZ2 (BIT_25|BIT_26)
/* 2048 word (2K) DRAM page size */
708
#define PAGSZ4 BIT_27
/* 4096 word (4K) DRAM page size */
709
#define PAGSZ8 (BIT_25|BIT_27)
/* 8192 word (8K) DRAM page size */
710
#define PAGSZ16 (BIT_26|BIT_27)
/* 16384 word (16K) DRAM page size */
711
#define PAGSZ32 (BIT_25|BIT_26|BIT_27)
/* 32768 word (32K) DRAM page size */
712
#define HIDMA BIT_30
/* Handshake Idle Cycle for DMA */
713
714
/* LAR Register */
715
#define A0LB0 0x00000000
/*Assign link buffer 0 to link port 0. */
716
#define A0LB1 BIT_0
/*Assign link buffer 0 to link port 1. */
717
#define A0LB2 BIT_1
/*Assign link buffer 0 to link port 2. */
718
#define A0LB3 (BIT_0|BIT_1)
/*Assign link buffer 0 to link port 3. */
719
#define A0LB4 BIT_2
/*Assign link buffer 0 to link port 4. */
720
#define A0LB5 (BIT_0|BIT_2)
/*Assign link buffer 0 to link port 5. */
721
#define A1LB0 0x00000000
/*Assign link buffer 0 to link port 0. */
722
#define A1LB1 BIT_3
/*Assign link buffer 1 to link port 1. */
723
#define A1LB2 BIT_4
/*Assign link buffer 1 to link port 2. */
724
#define A1LB3 (BIT_3|BIT_4)
/*Assign link buffer 1 to link port 3. */
725
#define A1LB4 BIT_5
/*Assign link buffer 1 to link port 4. */
726
#define A1LB5 (BIT_3|BIT_5)
/*Assign link buffer 1 to link port 5. */
727
#define A2LB0 0x00000000
/*Assign link buffer 2 to link port 0. */
728
#define A2LB1 BIT_6
/*Assign link buffer 2 to link port 1. */
729
#define A2LB2 BIT_7
/*Assign link buffer 2 to link port 2. */
730
#define A2LB3 (BIT_6|BIT_7)
/*Assign link buffer 2 to link port 3. */
731
#define A2LB4 BIT_8
/*Assign link buffer 2 to link port 4. */
732
#define A2LB5 (BIT_7|BIT_8)
/*Assign link buffer 2 to link port 5. */
733
#define A3LB0 0x00000000
/*Assign link buffer 3 to link port 0. */
734
#define A3LB1 BIT_9
/*Assign link buffer 3 to link port 1. */
735
#define A3LB2 BIT_10
/*Assign link buffer 3 to link port 2. */
736
#define A3LB3 (BIT_9|BIT_10)
/*Assign link buffer 3 to link port 3. */
737
#define A3LB4 BIT_11
/*Assign link buffer 3 to link port 4. */
738
#define A3LB5 (BIT_9|BIT_11)
/*Assign link buffer 3 to link port 5. */
739
#define A4LB0 0x00000000
/*Assign link buffer 4 to link port 0. */
740
#define A4LB1 BIT_12
/*Assign link buffer 4 to link port 1. */
741
#define A4LB2 BIT_13
/*Assign link buffer 4 to link port 2. */
742
#define A4LB3 (BIT_12|BIT_13)
/*Assign link buffer 4 to link port 3. */
743
#define A4LB4 BIT_14
/*Assign link buffer 4 to link port 4. */
744
#define A4LB5 (BIT_12|BIT_14)
/*Assign link buffer 4 to link port 5. */
745
#define A5LB0 0x00000000
/*Assign link buffer 5 to link port 0. */
746
#define A5LB1 BIT_15
/*Assign link buffer 5 to link port 1. */
747
#define A5LB2 BIT_16
/*Assign link buffer 5 to link port 2. */
748
#define A5LB3 (BIT_15|BIT_16)
/*Assign link buffer 5 to link port 3. */
749
#define A5LB4 BIT_17
/*Assign link buffer 5 to link port 4. */
750
#define A5LB5 (BIT_15|BIT_17)
/*Assign link buffer 5 to link port 5. */
751
752
753
/* LCTL0 Register */
754
#define L0EN BIT_0
/* LBUF0 Enable */
755
#define L0DEN BIT_1
/* LBUF0 DMA Enable */
756
#define L0CHEN BIT_2
/* LBUF0 DMA Chaining Enable */
757
#define L0TRAN BIT_3
/* LBUF0 Transmit (1=Transmit, 0=Receive) */
758
#define L0EXT BIT_4
/* LBUF0 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
759
#define L0CLKD0 BIT_5
/* LBUF0 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
760
#define L0CLKD1 BIT_6
/* LBUF0 Clock Divisor 1 (00 = 4) */
761
#define L0DMA2D BIT_7
/* LBUF0 2-Dimensional DMA Enable */
762
#define L0PDRDE BIT_8
/* LPORT0 Pulldown Resistor Disable */
763
#define L0DPWID BIT_9
/* LBUF0 Data Path Width (1 = 8-bit, 0 = 4-bit) */
764
765
#define L1EN BIT_10
/* LBUF1 Enable */
766
#define L1DEN BIT_11
/* LBUF1 DMA Enable */
767
#define L1CHEN BIT_12
/* LBUF1 DMA Chaining Enable */
768
#define L1TRAN BIT_13
/* LBUF1 Transmit (1=Transmit, 0=Receive) */
769
#define L1EXT BIT_14
/* LBUF1 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
770
#define L1CLKD0 BIT_15
/* LBUF1 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
771
#define L1CLKD1 BIT_16
/* LBUF1 Clock Divisor 1 (00 = 4) */
772
#define L1DMA2D BIT_17
/* LBUF1 2-Dimensional DMA Enable */
773
#define L1PDRDE BIT_18
/* LPORT1 Pulldown Resistor Disable */
774
#define L1DPWID BIT_19
/* LBUF1 Data Path Width (1 = 8-bit, 0 = 4-bit) */
775
776
#define L2EN BIT_20
/* LBUF2 Enable */
777
#define L2DEN BIT_21
/* LBUF2 DMA Enable */
778
#define L2CHEN BIT_22
/* LBUF2 DMA Chaining Enable */
779
#define L2TRAN BIT_23
/* LBUF2 Transmit (1=Transmit, 0=Receive) */
780
#define L2EXT BIT_24
/* LBUF2 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
781
#define L2CLKD0 BIT_25
/* LBUF2 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
782
#define L2CLKD1 BIT_26
/* LBUF2 Clock Divisor 1 (00 = 4) */
783
#define L2DMA2D BIT_27
/* LBUF2 2-Dimensional DMA Enable */
784
#define L2PDRDE BIT_28
/* LPORT2 Pulldown Resistor Disable */
785
#define L2DPWID BIT_29
/* LBUF2 Data Path Width (1 = 8-bit, 0 = 4-bit) */
786
787
788
/* LCTL1 Register */
789
#define L3EN BIT_0
/* LBUF3 Enable */
790
#define L3DEN BIT_1
/* LBUF3 DMA Enable */
791
#define L3CHEN BIT_2
/* LBUF3 DMA Chaining Enable */
792
#define L3TRAN BIT_3
/* LBUF3 Transmit (1=Transmit, 0=Receive) */
793
#define L3EXT BIT_4
/* LBUF3 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
794
#define L3CLKD0 BIT_5
/* LBUF3 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
795
#define L3CLKD1 BIT_6
/* LBUF3 Clock Divisor 1 (00 = 4) */
796
#define L3DMA2D BIT_7
/* LBUF3 2-Dimensional DMA Enable */
797
#define L3PDRDE BIT_8
/* LPORT3 Pulldown Resistor Disable */
798
#define L3DPWID BIT_9
/* LBUF3 Data Path Width (1 = 8-bit, 0 = 4-bit) */
799
800
#define L4EN BIT_10
/* LBUF4 Enable */
801
#define L4DEN BIT_11
/* LBUF4 DMA Enable */
802
#define L4CHEN BIT_12
/* LBUF4 DMA Chaining Enable */
803
#define L4TRAN BIT_13
/* LBUF4 Transmit (1=Transmit, 0=Receive) */
804
#define L4EXT BIT_14
/* LBUF4 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
805
#define L4CLKD0 BIT_15
/* LBUF4 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
806
#define L4CLKD1 BIT_16
/* LBUF4 Clock Divisor 1 (00 = 4) */
807
#define L4DMA2D BIT_17
/* LBUF4 2-Dimensional DMA Enable */
808
#define L4PDRDE BIT_18
/* LPORT4 Pulldown Resistor Disable */
809
#define L4DPWID BIT_19
/* LBUF4 Data Path Width (1 = 8-bit, 0 = 4-bit) */
810
811
#define L5EN BIT_20
/* LBUF5 Enable */
812
#define L5DEN BIT_21
/* LBUF5 DMA Enable */
813
#define L5CHEN BIT_22
/* LBUF5 DMA Chaining Enable */
814
#define L5TRAN BIT_23
/* LBUF5 Transmit (1=Transmit, 0=Receive) */
815
#define L5EXT BIT_24
/* LBUF5 Extended Word Size (1 = 48-bit, 0 = 32-bit)*/
816
#define L5CLKD0 BIT_25
/* LBUF5 Clock Divisor 0 (01 = 1, 10 = 2, 11 = 3) */
817
#define L5CLKD1 BIT_26
/* LBUF5 Clock Divisor 1 (00 = 4) */
818
#define L5DMA2D BIT_27
/* LBUF5 2-Dimensional DMA Enable */
819
#define L5PDRDE BIT_28
/* LPORT5 Pulldown Resistor Disable */
820
#define L5DPWID BIT_29
/* LBUF5 Data Path Width (1 = 8-bit, 0 = 4-bit) */
821
822
/* LCOM Register */
823
#define L0STAT0 BIT_0
/* LBUF0 Status 0 (11=full, 00=empty) */
824
#define L0STAT1 BIT_1
/* LBUF0 Status 1 (10=partially full, 01=reserved) */
825
#define L1STAT0 BIT_2
/* LBUF1 Status 0 (11=full, 00=empty) */
826
#define L1STAT1 BIT_3
/* LBUF1 Status 1 (10=partially full, 01=reserved) */
827
#define L2STAT0 BIT_4
/* LBUF2 Status 0 (11=full, 00=empty) */
828
#define L2STAT1 BIT_5
/* LBUF2 Status 1 (10=partially full, 01=reserved) */
829
#define L3STAT0 BIT_6
/* LBUF3 Status 0 (11=full, 00=empty) */
830
#define L3STAT1 BIT_7
/* LBUF3 Status 1 (10=partially full, 01=reserved) */
831
#define L4STAT0 BIT_8
/* LBUF2 Status 0 (11=full, 00=empty) */
832
#define L4STAT1 BIT_9
/* LBUF2 Status 1 (10=partially full, 01=reserved) */
833
#define L5STAT0 BIT_10
/* LBUF5 Status 0 (11=full, 00=empty) */
834
#define L5STAT1 BIT_11
/* LBUF5 Status 1 (10=partially full, 01=reserved) */
835
#define LRERR0 BIT_26
/* LBUF0 Rx Error Status (1=incomplete, 0=complete) */
836
#define LRERR1 BIT_27
/* LBUF1 Rx Error Status (1=incomplete, 0=complete) */
837
#define LRERR2 BIT_28
/* LBUF2 Rx Error Status (1=incomplete, 0=complete) */
838
#define LRERR3 BIT_29
/* LBUF3 Rx Error Status (1=incomplete, 0=complete) */
839
#define LRERR4 BIT_30
/* LBUF4 Rx Error Status (1=incomplete, 0=complete) */
840
#define LRERR5 BIT_31
/* LBUF5 Rx Error Status (1=incomplete, 0=complete) */
841
842
/* LSRQ Register */
843
#define L0TM BIT_4
/* LPORT0 Transmit Mask */
844
#define L0RM BIT_5
/* LPORT0 Receive Mask */
845
#define L1TM BIT_6
/* LPORT1 Transmit Mask */
846
#define L1RM BIT_7
/* LPORT1 Receive Mask */
847
#define L2TM BIT_8
/* LPORT2 Transmit Mask */
848
#define L2RM BIT_9
/* LPORT2 Receive Mask */
849
#define L3TM BIT_10
/* LPORT3 Transmit Mask */
850
#define L3RM BIT_11
/* LPORT3 Receive Mask */
851
#define L4TM BIT_12
/* LPORT4 Transmit Mask */
852
#define L4RM BIT_13
/* LPORT4 Receive Mask */
853
#define L5TM BIT_14
/* LPORT5 Transmit Mask */
854
#define L5RM BIT_15
/* LPORT5 Receive Mask */
855
#define L0TRQ BIT_20
/* LPORT0 Transmit Request Status */
856
#define L0RRQ BIT_21
/* LPORT0 Receive Request Status */
857
#define L1TRQ BIT_22
/* LPORT1 Transmit Request Status */
858
#define L1RRQ BIT_23
/* LPORT1 Receive Request Status */
859
#define L2TRQ BIT_24
/* LPORT2 Transmit Request Status */
860
#define L2RRQ BIT_25
/* LPORT2 Receive Request Status */
861
#define L3TRQ BIT_26
/* LPORT3 Transmit Request Status */
862
#define L3RRQ BIT_27
/* LPORT3 Receive Request Status */
863
#define L4TRQ BIT_28
/* LPORT4 Transmit Request Status */
864
#define L4RRQ BIT_29
/* LPORT4 Receive Request Status */
865
#define L5TRQ BIT_30
/* LPORT5 Transmit Request Status */
866
#define L5RRQ BIT_31
/* LPORT5 Receive Request Status */
867
868
/* STCTL0, STCTL1, SRCTL0, SRCTL1 registers */
869
#define SPEN BIT_0
/* SPORT enable primary A channel */
870
#define DTYPE0 0x00000000
/* right justify, fill unused MSBs with 0s */
871
#define DTYPE1 BIT_1
/* right justify, sign-extend into unused MSBs */
872
#define DTYPE2 BIT_2
/* compand using mu law */
873
#define DTYPE3 (BIT_1|BIT_2)
/* compand using a law */
874
#define SENDN BIT_3
/* MSB or LSB first */
875
#define SLEN3 BIT_5
/* serial length 3 */
876
#define SLEN4 (BIT_4|BIT_5)
/* serial length 4 */
877
#define SLEN5 BIT_6
/* serial length 5 */
878
#define SLEN6 (BIT_4|BIT_6)
/* serial length 6 */
879
#define SLEN7 (BIT_5|BIT_6)
/* serial length 7 */
880
#define SLEN8 (BIT_4|BIT_5|BIT_6)
/* serial length 8 */
881
#define SLEN9 BIT_7
/* serial length 9 */
882
#define SLEN10 (BIT_4|BIT_7)
/* serial length 10 */
883
#define SLEN11 (BIT_5|BIT_7)
/* serial length 11 */
884
#define SLEN12 (BIT_4|BIT_5|BIT_7)
/* serial length 12 */
885
#define SLEN13 (BIT_6|BIT_7)
/* serial length 13 */
886
#define SLEN14 (BIT_4|BIT_6|BIT_7)
/* serial length 14 */
887
#define SLEN15 (BIT_5|BIT_6|BIT_7)
/* serial length 15 */
888
#define SLEN16 (BIT_4|BIT_5|BIT_6|BIT_7)
/* serial length 16 */
889
#define SLEN17 BIT_8
/* serial length 17 */
890
#define SLEN18 (BIT_4|BIT_8)
/* serial length 18 */
891
#define SLEN19 (BIT_5|BIT_8)
/* serial length 19 */
892
#define SLEN20 (BIT_4|BIT_5|BIT_8)
/* serial length 20 */
893
#define SLEN21 (BIT_6|BIT_8)
/* serial length 21 */
894
#define SLEN22 (BIT_4|BIT_6|BIT_8)
/* serial length 22 */
895
#define SLEN23 (BIT_5|BIT_6|BIT_8)
/* serial length 23 */
896
#define SLEN24 (BIT_4|BIT_5|BIT_6|BIT_8)
/* serial length 24 */
897
#define SLEN25 (BIT_7|BIT_8)
/* serial length 25 */
898
#define SLEN26 (BIT_4|BIT_7|BIT_8)
/* serial length 26 */
899
#define SLEN27 (BIT_5|BIT_7|BIT_8)
/* serial length 27 */
900
#define SLEN28 (BIT_4|BIT_5|BIT_7|BIT_8)
/* serial length 28 */
901
#define SLEN29 (BIT_6|BIT_7|BIT_8)
/* serial length 29 */
902
#define SLEN30 (BIT_4|BIT_6|BIT_7|BIT_8)
/* serial length 30 */
903
#define SLEN31 (BIT_5|BIT_6|BIT_7|BIT_8)
/* serial length 31 */
904
#define SLEN32 (BIT_4|BIT_5|BIT_6|BIT_7|BIT_8)
/* serial length 32 */
905
#define PACK BIT_9
/* 16-to-32 data packing */
906
#define ICLK BIT_10
/* internally ('1') or externally ('0') generated transmit or recieve SCLKx */
907
#define CKRE BIT_12
/* Clock edge for data and frame sync sampling (rx) or driving (tx) */
908
#define TFSR BIT_13
/* transmit frame sync (FSx) required */
909
#define RFSR BIT_13
/* receive frame sync (FSx) required */
910
#define ITFS BIT_14
/* internally generated transmit frame sync (FSx) */
911
#define IRFS BIT_14
/* internally generated receive frame sync (FSx) */
912
#define DITFS BIT_15
/* (I2S & DSP serial modes only) Data Independent 'tx' FSx when DDIR bit = 1 */
913
#define IMODE BIT_15
/* Receive Mode comparison select (Multichannel only)*/
914
#define LTFS BIT_16
/* Active Low transmit frame sync (FSx) */
915
#define LRFS BIT_16
/* Active Low receive frame sync (FSx) */
916
#define LAFS BIT_17
/* Late (vs early) frame sync FSx */
917
#define SDEN BIT_18
/* SPORT TX DMA enable*/
918
#define SCHEN BIT_19
/* SPORT TX DMA chaining enable */
919
#define IMAT BIT_20
/* Multichannel Only - used in conjunction with IMODE bit */
920
#define D2FDMA BIT_21
/* Two Dimension DMA Array Enable*/
921
#define SPL BIT_22
/* Serial Port Loopback Enable*/
922
#define MCE BIT_23
/* Multichannel Enable*/
923
#define MFD1 BIT_20
/* Multichannel Transmit Frame Sync Delay 1*/
924
#define MFD2 BIT_21
/* Multichannel Transmit Frame Sync Delay 2*/
925
#define MFD3 (BIT_20|BIT_21)
/* Multichannel Transmit Frame Sync Delay 3*/
926
#define MFD4 BIT_22
/* Multichannel Transmit Frame Sync Delay 4*/
927
#define MFD5 (BIT_20|BIT_22)
/* Multichannel Transmit Frame Sync Delay 5*/
928
#define MFD6 (BIT_21|BIT_22)
/* Multichannel Transmit Frame Sync Delay 6*/
929
#define MFD7 (BIT_20|BIT_21|BIT_22)
/* Multichannel Transmit Frame Sync Delay 7*/
930
#define MFD8 BIT_23
/* Multichannel Transmit Frame Sync Delay 8*/
931
#define MFD9 (BIT_20|BIT_23)
/* Multichannel Transmit Frame Sync Delay 2*/
932
#define MFD10 (BIT_21|BIT_23)
/* Multichannel Transmit Frame Sync Delay 3*/
933
#define MFD11 (BIT_20|BIT_21|BIT_23)
/* Multichannel Transmit Frame Sync Delay 4*/
934
#define MFD12 (BIT_22|BIT_23)
/* Multichannel Transmit Frame Sync Delay 5*/
935
#define MFD13 (BIT_20|BIT_21|BIT_23)
/* Multichannel Transmit Frame Sync Delay 6*/
936
#define MFD14 (BIT_21|BIT_22|BIT_23)
/* Multichannel Transmit Frame Sync Delay 7*/
937
#define MFD15 (BIT_20|BIT_21|BIT_22|BIT_23)
/* Multichannel Transmit Frame Sync Delay 8*/
938
#define NCH0 0x00000000
/* 1 Channel */
939
#define NCH1 BIT_24
/* 2 Channels */
940
#define NCH2 BIT_25
/* 3 Channels */
941
#define NCH3 (BIT_24|BIT_25)
/* 4 Channels */
942
#define NCH4 BIT_26
/* 5 Channels */
943
#define NCH5 (BIT_24|BIT_26)
/* 6 Channels */
944
#define NCH6 (BIT_25|BIT_26)
/* 7 Channels */
945
#define NCH7 (BIT_24|BIT_25|BIT_26)
/* 8 Channels */
946
#define NCH8 BIT_27
/* 9 Channels */
947
#define NCH9 (BIT_24|BIT_27)
/* 10 Channels */
948
#define NCH10 (BIT_25|BIT_27)
/* 11 Channels */
949
#define NCH11 (BIT_24|BIT_25|BIT_27)
/* 12 Channels */
950
#define NCH12 (BIT_26|BIT_27)
/* 13 Channels */
951
#define NCH13 (BIT_24|BIT_26|BIT_27)
/* 14 Channels */
952
#define NCH14 (BIT_25|BIT_26|BIT_27)
/* 15 Channels */
953
#define NCH15 (BIT_24|BIT_25|BIT_26|BIT_27)
/* 16 Channels */
954
#define NCH16 BIT_28
/* 17 Channels */
955
#define NCH17 (BIT_24|BIT_28)
/* 18 Channels */
956
#define NCH18 (BIT_25|BIT_28)
/* 19 Channels */
957
#define NCH19 (BIT_24|BIT_25|BIT_28)
/* 20 Channels */
958
#define NCH20 (BIT_26|BIT_28)
/* 21 Channels */
959
#define NCH21 (BIT_24|BIT_26|BIT_28)
/* 22 Channels */
960
#define NCH22 (BIT_25|BIT_26|BIT_28)
/* 23 Channels */
961
#define NCH23 (BIT_24|BIT_25|BIT_26|BIT_28)
/* 24 Channels */
962
#define NCH24 (BIT_27|BIT_28)
/* 25 Channels */
963
#define NCH25 (BIT_24|BIT_27|BIT_28)
/* 26 Channels */
964
#define NCH26 (BIT_25|BIT_27|BIT_28)
/* 27 Channels */
965
#define NCH27 (BIT_24|BIT_25|BIT_27|BIT_28)
/* 28 Channels */
966
#define NCH28 (BIT_26|BIT_27|BIT_28)
/* 29 Channels */
967
#define NCH29 (BIT_24|BIT_26|BIT_27|BIT_28)
/* 30 Channels */
968
#define NCH30 (BIT_25|BIT_26|BIT_27|BIT_28)
/* 31 Channels */
969
#define NCH31 (BIT_24|BIT_25|BIT_26|BIT_27|BIT_28)
/* 32 Channels */
970
#define CHNL0 0x00000000
/* Channel 0 Selected (Read Only)*/
971
#define CHNL1 BIT_24
/* Channel 1 Selected (Read Only)*/
972
#define CHNL2 BIT_25
/* Channel 2 Selected (Read Only)*/
973
#define CHNL3 (BIT_24|BIT_25)
/* Channel 3 Selected (Read Only)*/
974
#define CHNL4 BIT_26
/* Channel 4 Selected (Read Only)*/
975
#define CHNL5 (BIT_24|BIT_26)
/* Channel 5 Selected (Read Only)*/
976
#define CHNL6 (BIT_25|BIT_26)
/* Channel 6 Selected (Read Only)*/
977
#define CHNL7 (BIT_24|BIT_25|BIT_26)
/* Channel 7 Selected (Read Only)*/
978
#define CHNL8 BIT_27
/* Channel 8 Selected (Read Only)*/
979
#define CHNL9 (BIT_24|BIT_27)
/* Channel 9 Selected (Read Only)*/
980
#define CHNL10 (BIT_25|BIT_27)
/* Channel 10 Selected (Read Only)*/
981
#define CHNL11 (BIT_24|BIT_25|BIT_27)
/* Channel 11 Selected (Read Only)*/
982
#define CHNL12 (BIT_26|BIT_27)
/* Channel 12 Selected (Read Only)*/
983
#define CHNL13 (BIT_24|BIT_26|BIT_27)
/* Channel 13 Selected (Read Only)*/
984
#define CHNL14 (BIT_25|BIT_26|BIT_27)
/* Channel 14 Selected (Read Only)*/
985
#define CHNL15 (BIT_24|BIT_25|BIT_26|BIT_27)
/* Channel 15 Selected (Read Only)*/
986
#define CHNL16 BIT_28
/* Channel 16 Selected (Read Only)*/
987
#define CHNL17 (BIT_24|BIT_28)
/* Channel 17 Selected (Read Only)*/
988
#define CHNL18 (BIT_25|BIT_28)
/* Channel 18 Selected (Read Only)*/
989
#define CHNL19 (BIT_24|BIT_25|BIT_28)
/* Channel 19 Selected (Read Only)*/
990
#define CHNL20 (BIT_26|BIT_28)
/* Channel 20 Selected (Read Only)*/
991
#define CHNL21 (BIT_24|BIT_26|BIT_28)
/* Channel 21 Selected (Read Only)*/
992
#define CHNL22 (BIT_25|BIT_26|BIT_28)
/* Channel 22 Selected (Read Only)*/
993
#define CHNL23 (BIT_24|BIT_25|BIT_26|BIT_28)
/* Channel 23 Selected (Read Only)*/
994
#define CHNL24 (BIT_27|BIT_28)
/* Channel 24 Selected (Read Only)*/
995
#define CHNL25 (BIT_24|BIT_27|BIT_28)
/* Channel 25 Selected (Read Only)*/
996
#define CHNL26 (BIT_25|BIT_27|BIT_28)
/* Channel 26 Selected (Read Only)*/
997
#define CHNL27 (BIT_24|BIT_25|BIT_27|BIT_28)
/* Channel 27 Selected (Read Only)*/
998
#define CHNL28 (BIT_26|BIT_27|BIT_28)
/* Channel 28 Selected (Read Only)*/
999
#define CHNL29 (BIT_24|BIT_26|BIT_27|BIT_28)
/* Channel 29 Selected (Read Only)*/
1000
#define CHNL30 (BIT_25|BIT_26|BIT_27|BIT_28)
/* Channel 30 Selected (Read Only)*/
1001
#define CHNL31 (BIT_24|BIT_25|BIT_26|BIT_27|BIT_28)
/* Channel 31 Selected (Read Only)*/
1002
#define ROVF BIT_29
/* Receive Overflow Status (Read Only)*/
1003
#define RXSEmpty 0x00000000
/* Transmit Data Buffer Empty (Read Only)*/
1004
#define RXSParial BIT_31
/* Transmit Data Partially Full (Read Only)*/
1005
#define RXSFull (BIT_30|BIT_31)
/* Transmit Data Full (Read Only)*/
1006
#define TUVF BIT_29
/* Transmit Underflow Status (Read Only)*/
1007
#define TXSEmpty 0x00000000
/* Transmit Data Buffer Empty (Read Only)*/
1008
#define TXSParial BIT_31
/* Transmit Data Partially Full (Read Only)*/
1009
#define TXSFull (BIT_30|BIT_31)
/* Transmit Data Full (Read Only)*/
1010
1011
/*DMACx Registers*/
1012
#define DEN BIT_0
/* External port DMA enable */
1013
#define CHEN BIT_1
/* External port DMA chaining enable */
1014
#define TRAN BIT_2
/* External port transmit/receive select */
1015
#define PS0 0x00000000
/* External port packing status, pack complete (Read only) */
1016
#define PS1 BIT_3
/* External port packing status, 1st stage pack (Read only) */
1017
#define PS2 BIT_4
/* External port packing status, 2nd stage multi-stage pack (Read only) */
1018
#define DTYPE BIT_5
/* External port data type select */
1019
#define PMODE0 0x00000000
/* External port packing mode - no pack */
1020
#define PMODE1 BIT_6
/* External port packing mode - 16 external to 32/64 internal */
1021
#define PMODE2 BIT_7
/* External port packing mode - 16 external to 48 internal */
1022
#define PMODE3 (BIT_6|BIT_7)
/* External port packing mode - 32 external to 48 internal */
1023
#define PMODE4 BIT_8
/* External port packing mode - 32 external to 32/64 internal */
1024
#define MSWF BIT_9
/* Most significant 16-bit word first during packing */
1025
#define MASTER BIT_10
/* Master mode enable */
1026
#define HSHAKE BIT_11
/* Handshake mode enable */
1027
#define INTIO BIT_12
/* Single-word interrupt enable */
1028
#define EXT_HANDSHAKE_EN BIT_13
/* External handshake mode enable */
1029
#define FLSH BIT_14
/* Flush DMA buffers and status */
1030
#define PRIO BIT_15
/* External port bus priority */
1031
#define FSe 0x00000000
/* External port FIFO buffer status - empty (read only) */
1032
#define FSnf BIT_16
/* External port FIFO buffer status - not full (read only) */
1033
#define FSne BIT_17
/* External port FIFO buffer status - not empty (read only) */
1034
#define FSf (BIT_16|BIT_17)
/* External port FIFO buffer status - full (read only) */
1035
#define INT32 BIT_18
/* Internal memory 32-bit tranfers select */
1036
#define MAXBL BIT_19
/* Maximum burst length select */
1037
1038
#endif
1039
1040
Generated on Tue Mar 31 2020 13:10:44 for NSCL DDAS by
1.8.8
1.8.8
