sis330x

Module base address in VME.

Module clock source. This must be a value chosen from one of the following strings: 100Mhz, 50Mhz, 25Mhz, 12.5Mhz, 6.25Mhz, 3.125Mhz FrontPanel P2Connector. The clock source determines the sampling rate of the ADC (or when data are clocked in in the case of HiRA Mode.

If true the start delay is enabled and. See -startdelayticks to see how this delay is controlled. Note that the start delay determines when the first sample is saved relative to the start.

Number of samples in the start delay. If -startdelay is false, this parameter is not used.

If true, the stop delay is enabled. See -stopdelayticks to set the actual stop delay.

This is the number of samples in the stop delay. If -stopdelay is true, when a stop occurs, data will be taken for this number of samples more. Note that this value is completely ignored if -stopdelay is false.

If true the module stop is the trigger. This pretty much has to be used with -stopdelay and -stopdelayticks

Module is or is not in gate mode. In gate mode the module is started from the falling edge of the gate input and stopped by the rising edge of that signal.

Start/Stop come from lemo inputs. This is enabled by default.

Backplane signals on the p2 connector provide start/stop. Note that this and lemostartstop are not mutually exlusive.

If true, HiRA random clock mode is enabled. HiRA Random clock is normally used with the Washington University Chip board readouts when the readout is done with an XLM other than the XLM-VV when the analog information is collected by an SIS 3301 board.

If true front panel provides a random clock with a symmetric pulse shape See section2.5.3 of the module documentation.

Size of sample buffers. This is one of the following text strings: 128K, 16K, 4K, 2K, 1K, 512, 256 128.

Buffers are in wrap mode (normally used if start/stop is longer than the samplesize. Once sampling runs off the end of the buffer sampling continues writing at the low memory location (wraps). Please note that at present, the readout method used does not support this. If you have a need to use this mode, please contact the NSCL software development group to arrange further development.

If true, channel thresholds represent a level _below_ which the conversion must fall. This is normally used with negative going pulses since the data are represented as half-scale offset unsigned integers.

Threshold values for all 8 channels. This parameter, if provided is an 8 element integer list of threshold values. See as well thresholdslt which can modify how this value is interpreted.

List of flags indicating which groups of ADCs will be read. The module is organized into 4 groups of 2 ADCs each). The manual refers to them as groups 1,2,3,4. The first list element allows or disables the readout of group 1 and so on.