tdc1x90 -- Provide support for the CAEN V1x90 TDC family.


tdc1x90 create name ?options...?

tdc1x90 config name ?options?

tdc1x90 cget name


Creates, configures and introspects CAEN V1x90 TDCs. These modules are only supported in trigger matching mode. Note that the trigger time is only good to the FPGA clock, to get precise trigger relative timing you will need to also digitize the trigger itself. SpecTcl supports doing a digital subtraction of the trigger channel from all other channels to get precise trigger relative timing.

The create subcommand creates a new TDC named name the options... optional parameter are configuration option value pairs as described in OPTIONS below. The config subcommand locates the TDC named name and further configures it via the options described in OPTIONS below.

The cget subcommand returns as a value the module configuration. The configurationis returned as a list. Each element of the list is a two element sublist consisting of the configuration option name and its current value.


-base base-address

provides the module base address as set by the rotary switches on the board.

-vsn geo

Provides the virtual slot number. This value will appear in the data from the module in the GEO field. The geo value must be between 0 and 31 inclusive.

-ipl n

Sets the interrupt priority level when using the device interrupts. If this is 0 interrupts are disabled. Legal value are between 0 and 7 inclusive. See the -vector switch as well. This defaults to 0.

-vector nnn

Sets the interrrupt status id value for the module if used in interrupt mode. If this is 0, interrupts are disabled. See -ipl as well. This defaults to 0. The values must be integers in the range 0 - 255 inclusive.

-termination none|switch|on

Sets the module termination. The value can be any of the following:


No termination will be supplied by the module.


Termination will be controlled by switches in the module


Termination is enabled.

The default is on

-tagtime on|off

Controls wehther or not the trigger time will be inlcuded in the data. Note that the trigger time is only accurate to within one tick of the 80Mhz FPGA clock.

-highwatermark n

Determines the numbger of events that must be buffered by the TDC to generate an interrupt. The vale must be an integer in the range 0..65535 inclusive. The default value 1, means an interrupt is generated whenever there is at least one event in the TDC and the TDC interrupts are enabled.

-ecloutput ready|full|almostfull|error

Determines which signal is presented at the programmable ECL output pins. See the CAEN V1190/1290 manuals for information about the possible values. The default is ready

-window n

The width of the trigger matching window in 25ns units. This is sets the effective range of the TDC when simulating a common stop or common start TDC. See also -offset, -extramargin and -rejectmargin and see the section of the TDC manual that describes trigger matching mode. The default value is 40 which corresponds to a 1usec matching window.

-offset n

Determines when the trigger matching window starts relative to the gate. A positive offset starts the match window after the gate while a negative offset starts the match window prior to the gate. The values are integers and are in 25ns units. See section 2.4.1 for additional constraints. Note that the actual window start time will jitter by +/-25ns, and therefore you should use a reference channel to get good gate relative timing. Values must be in the range -2048 to 40 inclusive... Defaults to -40 or 1usec prior to the gate.

-extramargin n

The extra search margin for hits. This is the addtional time during after the matching window during which the module will search for hits that are within the window before declaring the event. This is needed because hits are searched for in the module's L1 buffer. Contention may prevent matching hits from being written to the L1 buffer for some time after they have actually occured. See 2.4.1 in the manual. The units of this value are also 25ns. Defaults to 8 which is 200ns.

-rejectmargin n

The reject margin. This is also in 25ns units. While the module is in continuous storage, it maintains a reject counter that flushes hits from the buffer when the trigger window is not active. The module will only retain hits for the width of the trigger window + offset + reject marjin before throwing them away if there is no trigger. This ensures the TDC buffer does not overflow and that the search for matching hits on the trigger is rapid. Defaults to 4 which is 100ns.

-triggerrelative enabled|disabled

If enabled, the trigger time is subtracted from all the hits. Note again that the trigger time is only precise to 25ns. Precise timing relative to the trigger can only be done by subtracting a digitized trigger time from the hits. Defaults to enabled

-edgedetect pair | leading | trailing | both

Sets the module edge detect mode. Figure 2.2 provides trailing, both} documentation about what this means; 'pair' provides the width of a pulse in a channel, 'leading' provides a hit time at the leading edge of a pulse, 'trailing' provides a hit time at the trailing edge of an input pulse, and 'both' provides the time of both the leading and trailing edges of a pulse Defaults to leading.

-edgeresolution 800ps | 200ps | 100sp | 25ps

Selects the resolution for the leading/trailing resolution. It is an error to use 25ps if the module is not a V1290 Defaults to 100ps

-leresolution 100ps | 200ps | 400ps | 800ps | 1.6ns | 3.12ns | 6.25ns | 12.5ns

In leading, trailing and both mode, sets the resolution with which the leading edge is detected. Defaults to: 100ps.

-widthresolution 100ps | 200ps | 400ops | 800ps | 1.6ns | 3.2ns | 6.25ns | 12.5ns | 400ns | 800ns

Sets the resolution with which a pulse width is measured in pair mode. defaults to 100ps

-deadtime 5ns | 10ns | 30ns | Sets 100ns

the double hit resolution. Defaults to 5ns

-encapsulatechip true | false

If true, the data from a chip is encapsulated as shown in figures 6.2/6.4 by a TDC Chip header/trailer. default enabled

-maxhits 0 | 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | infinite

Specifies the maximum number of hits for each TDC chip in an event. Note that a TDC chip has 32 channels.

-errormark true | false

If true, when an error is detected, an error mark item is placed in the output buffer. Figure 6.5 describes the format of this item. Defaults to true

-errorbypass on | off

If enabled, a TDC that reports an error will not be read out for that event. Default: on

-globaloffset {n m}

Provides the global offset/vernier offset. Default: {0 0}


Arbitary number of elements that can adjust the value of individual channels by adding a positive offset to them. The value of this is a list of two element lists where each element consist of a channel number and its offset. e.g. {{10 6} {32 5}} sets the channel offsets for channel 10 to 6 and for channel 32 to 5.

-refchannel n

Sets the reference channel. The value of this channel is subtracted from all other channels to produce high precision times. Defaults to 0. This option is only used by SpecTcl and does not influence the way the TDC is initialized or read.

-depth n

Sets the number of hits to retain for each channel for the purposes of histogramming. Defaults to 16. This option is only processed by SpecTcl. It setting does not influence the setup or readout of the TDC. Note however that setting this value larger than the value of -maxhits is probably not very useful.

-channelcount n

Sets the number of channels the model of the TDC being used has. This is only used to setup SpecTcl's histogramming. The value should be one of 16, 32, 64, or 128, however this is not checked by the processing code for this option.


create name base

Creates a new instance of a CAEN multihit TDC from the V1x90 family of digitizers. name is used to refer to this module from now on. The base sets the base address of the module.

config name options

Configures an existing TDC name options are option name value pairs described above.

cget name

Returns the module name's configuration as a list of name value pairs.