NSCL DDAS  1.0
Support for XIA DDAS at the NSCL
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ModuleSettings.h
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1 /*
2  This software is Copyright by the Board of Trustees of Michigan
3  State University (c) Copyright 2017.
4 
5  You may use this software under the terms of the GNU public license
6  (GPL). The terms of this license are described at:
7 
8  http://www.gnu.org/licenses/gpl.txt
9 
10  Authors:
11  Ron Fox
12  Giordano Cerriza
13  NSCL
14  Michigan State University
15  East Lansing, MI 48824-1321
16 */
17 
21 #ifndef MODULESETTINGS_H
22 #define MODULESETTINGS_H
23 #include <stdint.h>
24 #include <string>
25 #include <vector>
26 
27 namespace DDAS {
28 
29 
34  static const unsigned CHANNELS(16);
35 
36  struct ModuleSettings {
37  // Per module parameters:
38 
39  unsigned int s_csra; /* CSRA Bitmask */
40  unsigned int s_csrb; /* CSRB Bitmask */
41  unsigned int s_format; /* Module format */
42  unsigned int s_maxEvents; /* Module max events */
43  bool s_synchWait; /* Wait for synchronization */
44  bool s_inSynch; /* Synchronized */
45  unsigned int s_SlowFilterRange;
46  unsigned int s_FastFilterRange;
47  unsigned int s_FastTrgBackPlaneEnables;
48  unsigned int s_trigConfig0;
49  unsigned int s_trigConfig1;
50  unsigned int s_trigConfig2;
51  unsigned int s_trigConfig3;
52  unsigned int s_HostRtPreset;
53 
54  // Per channel parameters... these are all doubles.
55 
56  double s_triggerRiseTime[CHANNELS];
57  double s_triggerFlattop[CHANNELS];
58  double s_triggerThreshold[CHANNELS];;
59  double s_energyRiseTime[CHANNELS];
60  double s_energyFlattop[CHANNELS];
61  double s_tau[CHANNELS];
62  double s_traceLength[CHANNELS];
63  double s_traceDelay[CHANNELS];
64  double s_vOffset[CHANNELS];
65  double s_Xdt[CHANNELS];
66  double s_BaselinePct[CHANNELS];
67  uint32_t s_Emin[CHANNELS];
68  uint32_t s_binFactor[CHANNELS];
69  uint32_t s_baselineAverage[CHANNELS];
70  uint32_t s_chanCsra[CHANNELS];
71  uint32_t s_chanCsrb[CHANNELS];
72  double s_blCut[CHANNELS];
73  double s_fastTrigBackLen[CHANNELS];
74  double s_CFDDelay[CHANNELS];
75  double s_CFDScale[CHANNELS];
76  double s_CFDThreshold[CHANNELS];
77  double s_QDCLen0[CHANNELS];
78  double s_QDCLen1[CHANNELS];
79  double s_QDCLen2[CHANNELS];
80  double s_QDCLen3[CHANNELS];
81  double s_QDCLen4[CHANNELS];
82  double s_QDCLen5[CHANNELS];
83  double s_QDCLen6[CHANNELS];
84  double s_QDCLen7[CHANNELS];
85  double s_extTrigStretch[CHANNELS];
86  double s_vetoStretch[CHANNELS];
87  uint32_t s_multiplicityMaskL[CHANNELS];
88  uint32_t s_multiplicityMaskH[CHANNELS];
89  double s_externDelayLen[CHANNELS];
90  double s_FTrigoutDelay[CHANNELS];
91  double s_chanTriggerStretch[CHANNELS];
92  };
93 
98  struct Slot {
99  unsigned s_slotNum;
100  ModuleSettings s_settings;
101  };
106  struct Crate {
107  unsigned s_crateId;
108  std::vector<Slot> s_slots;
109  };
110 } // Namespace DDAS
111 
112 #endif
DDAS::Slot
Definition: ModuleSettings.h:98
DDAS::ModuleSettings
Definition: ModuleSettings.h:36
DDAS::Crate
Definition: ModuleSettings.h:106
DDAS
Definition: functions.h:26
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