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xiaapi
inc
Reg9054.h
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#ifndef __REG9054_H
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#define __REG9054_H
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/*******************************************************************************
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* Copyright (c) PLX Technology, Inc.
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*
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* PLX Technology Inc. licenses this source file under the GNU Lesser General Public
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* License (LGPL) version 2. This source file may be modified or redistributed
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* under the terms of the LGPL and without express permission from PLX Technology.
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*
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* PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY,
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* EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee
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* or representations regarding the use of, or the results of the use of,
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* the software and documentation in terms of correctness, accuracy,
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* reliability, currentness, or otherwise; and you rely on the software,
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* documentation and results solely at your own risk.
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*
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* IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
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* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
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* OF ANY KIND.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* File Name:
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*
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* Reg9054.h
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*
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* Description:
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*
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* This file defines all the PLX 9054 chip Registers.
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*
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* Revision:
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*
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* 11-01-06 : PLX SDK v5.00
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*
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******************************************************************************/
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#include "PciRegs.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#if defined(PLX_LOCAL_CODE)
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#define PCI9054_REG_BASE 0x080
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#define PCI9054_NEW_CAP_BASE 0x140
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#define PCI9054_MAX_REG_OFFSET 0x194
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#else
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#define PCI9054_REG_BASE 0x000
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#define PCI9054_NEW_CAP_BASE 0x000
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#define PCI9054_MAX_REG_OFFSET 0x100
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#endif
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// Additional defintions
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#define PCI9054_EEPROM_SIZE 0x058 // EEPROM size (bytes) used by PLX Chip
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#define PCI9054_DMA_CHANNELS 2 // Number of DMA channels supported by PLX Chip
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// PCI Configuration Registers
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#define PCI9054_VENDOR_ID CFG_VENDOR_ID
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#define PCI9054_COMMAND CFG_COMMAND
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#define PCI9054_REV_ID CFG_REV_ID
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#define PCI9054_CACHE_SIZE CFG_CACHE_SIZE
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#define PCI9054_RTR_BASE CFG_BAR0
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#define PCI9054_RTR_IO_BASE CFG_BAR1
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#define PCI9054_LOCAL_BASE0 CFG_BAR2
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#define PCI9054_LOCAL_BASE1 CFG_BAR3
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#define PCI9054_UNUSED_BASE1 CFG_BAR4
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#define PCI9054_UNUSED_BASE2 CFG_BAR5
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#define PCI9054_CIS_PTR CFG_CIS_PTR
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#define PCI9054_SUB_ID CFG_SUB_VENDOR_ID
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#define PCI9054_EXP_ROM_BASE CFG_EXP_ROM_BASE
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#define PCI9054_CAP_PTR CFG_CAP_PTR
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#define PCI9054_RESERVED2 CFG_RESERVED1
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#define PCI9054_INT_LINE CFG_INT_LINE
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#define PCI9054_PM_CAP_ID (PCI9054_NEW_CAP_BASE + 0x040)
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#define PCI9054_PM_CSR (PCI9054_NEW_CAP_BASE + 0x044)
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#define PCI9054_HS_CAP_ID (PCI9054_NEW_CAP_BASE + 0x048)
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#define PCI9054_VPD_CAP_ID (PCI9054_NEW_CAP_BASE + 0x04c)
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#define PCI9054_VPD_DATA (PCI9054_NEW_CAP_BASE + 0x050)
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// Local Configuration Registers
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#define PCI9054_SPACE0_RANGE (PCI9054_REG_BASE + 0x000)
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#define PCI9054_SPACE0_REMAP (PCI9054_REG_BASE + 0x004)
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#define PCI9054_LOCAL_DMA_ARBIT (PCI9054_REG_BASE + 0x008)
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#define PCI9054_ENDIAN_DESC (PCI9054_REG_BASE + 0x00c)
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#define PCI9054_EXP_ROM_RANGE (PCI9054_REG_BASE + 0x010)
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#define PCI9054_EXP_ROM_REMAP (PCI9054_REG_BASE + 0x014)
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#define PCI9054_SPACE0_ROM_DESC (PCI9054_REG_BASE + 0x018)
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#define PCI9054_DM_RANGE (PCI9054_REG_BASE + 0x01c)
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#define PCI9054_DM_MEM_BASE (PCI9054_REG_BASE + 0x020)
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#define PCI9054_DM_IO_BASE (PCI9054_REG_BASE + 0x024)
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#define PCI9054_DM_PCI_MEM_REMAP (PCI9054_REG_BASE + 0x028)
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#define PCI9054_DM_PCI_IO_CONFIG (PCI9054_REG_BASE + 0x02c)
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#define PCI9054_SPACE1_RANGE (PCI9054_REG_BASE + 0x0f0)
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#define PCI9054_SPACE1_REMAP (PCI9054_REG_BASE + 0x0f4)
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#define PCI9054_SPACE1_DESC (PCI9054_REG_BASE + 0x0f8)
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#define PCI9054_DM_DAC (PCI9054_REG_BASE + 0x0fc)
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// Runtime Registers
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#if defined(PLX_LOCAL_CODE)
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#define PCI9054_MAILBOX0 0x0c0
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#define PCI9054_MAILBOX1 0x0c4
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#else
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#define PCI9054_MAILBOX0 0x078
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#define PCI9054_MAILBOX1 0x07c
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#endif
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#define PCI9054_MAILBOX2 (PCI9054_REG_BASE + 0x048)
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#define PCI9054_MAILBOX3 (PCI9054_REG_BASE + 0x04c)
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#define PCI9054_MAILBOX4 (PCI9054_REG_BASE + 0x050)
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#define PCI9054_MAILBOX5 (PCI9054_REG_BASE + 0x054)
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#define PCI9054_MAILBOX6 (PCI9054_REG_BASE + 0x058)
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#define PCI9054_MAILBOX7 (PCI9054_REG_BASE + 0x05c)
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#define PCI9054_LOCAL_DOORBELL (PCI9054_REG_BASE + 0x060)
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#define PCI9054_PCI_DOORBELL (PCI9054_REG_BASE + 0x064)
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#define PCI9054_INT_CTRL_STAT (PCI9054_REG_BASE + 0x068)
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#define PCI9054_EEPROM_CTRL_STAT (PCI9054_REG_BASE + 0x06c)
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#define PCI9054_PERM_VENDOR_ID (PCI9054_REG_BASE + 0x070)
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#define PCI9054_REVISION_ID (PCI9054_REG_BASE + 0x074)
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// DMA Registers
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#define PCI9054_DMA0_MODE (PCI9054_REG_BASE + 0x080)
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#define PCI9054_DMA0_PCI_ADDR (PCI9054_REG_BASE + 0x084)
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#define PCI9054_DMA0_LOCAL_ADDR (PCI9054_REG_BASE + 0x088)
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#define PCI9054_DMA0_COUNT (PCI9054_REG_BASE + 0x08c)
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#define PCI9054_DMA0_DESC_PTR (PCI9054_REG_BASE + 0x090)
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#define PCI9054_DMA1_MODE (PCI9054_REG_BASE + 0x094)
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#define PCI9054_DMA1_PCI_ADDR (PCI9054_REG_BASE + 0x098)
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#define PCI9054_DMA1_LOCAL_ADDR (PCI9054_REG_BASE + 0x09c)
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#define PCI9054_DMA1_COUNT (PCI9054_REG_BASE + 0x0a0)
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#define PCI9054_DMA1_DESC_PTR (PCI9054_REG_BASE + 0x0a4)
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#define PCI9054_DMA_COMMAND_STAT (PCI9054_REG_BASE + 0x0a8)
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#define PCI9054_DMA_ARBIT (PCI9054_REG_BASE + 0x0ac)
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#define PCI9054_DMA_THRESHOLD (PCI9054_REG_BASE + 0x0b0)
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#define PCI9054_DMA0_PCI_DAC (PCI9054_REG_BASE + 0x0b4)
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#define PCI9054_DMA1_PCI_DAC (PCI9054_REG_BASE + 0x0b8)
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// Messaging Unit Registers
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#define PCI9054_OUTPOST_INT_STAT (PCI9054_REG_BASE + 0x030)
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#define PCI9054_OUTPOST_INT_MASK (PCI9054_REG_BASE + 0x034)
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#define PCI9054_MU_CONFIG (PCI9054_REG_BASE + 0x0c0)
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#define PCI9054_FIFO_BASE_ADDR (PCI9054_REG_BASE + 0x0c4)
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#define PCI9054_INFREE_HEAD_PTR (PCI9054_REG_BASE + 0x0c8)
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#define PCI9054_INFREE_TAIL_PTR (PCI9054_REG_BASE + 0x0cc)
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#define PCI9054_INPOST_HEAD_PTR (PCI9054_REG_BASE + 0x0d0)
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#define PCI9054_INPOST_TAIL_PTR (PCI9054_REG_BASE + 0x0d4)
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#define PCI9054_OUTFREE_HEAD_PTR (PCI9054_REG_BASE + 0x0d8)
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#define PCI9054_OUTFREE_TAIL_PTR (PCI9054_REG_BASE + 0x0dc)
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#define PCI9054_OUTPOST_HEAD_PTR (PCI9054_REG_BASE + 0x0e0)
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#define PCI9054_OUTPOST_TAIL_PTR (PCI9054_REG_BASE + 0x0e4)
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#define PCI9054_FIFO_CTRL_STAT (PCI9054_REG_BASE + 0x0e8)
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#ifdef __cplusplus
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}
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#endif
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#endif
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